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參數(shù)資料
| 型號(hào)： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 97/146頁(yè) |
| 文件大小： | 852K |
| 代理商： | MC68HC05L16CFU |
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Parallel Input/Output (I/O)
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
54
Freescale Semiconductor
The PC4 and PC3 pins share functions with the timer input pins (EVI and TCAP). These bits are not
affected by the usage of timer input functions and the directions of pins are always controlled by the
DDRC4 and DDRC3 bits. Also, the DDRC4 and DDRC3 bits determine whether the pin states or data
latch states should be read by the CPU.
NOTE
Since the TCAP pin is shared with the PC3 I/O pin, changing the state of
the PC3 DDR or data register can cause an unwanted TCAP interrupt. This
can be handled by clearing the ICIE bit before changing the configuration
of PC3 and clearing any pending interrupts before enabling ICIE.
Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be
cleared whenever EVI is used. EVI should not be used when DDRC4 is
high.
The PC2–PC0 pins are shared with the simple serial peripheral interface (SSPI). When the SSPI is not
used (SPE = 0), DDRC2–DDRC0 bits control the direction of the pins, and when the SSPI is enabled, the
pins are configured as serial clock output or input (SCK), serial data output (SDO), and serial data input
(SDI). The direction of the SCK depends on the MSTR bit in the SPCR. When PORTC is read, the value
read will be determined by the data direction register. When the port is configured for input (DDRC2,
DDRC1, or DDRC0 equal to logic 0) the pin state is read. When the port is configured for output (DDRC2,
DDRC1, or DDRC0 equal to logic 0), the output data latch is read.
Port C has optional pullup resistors. When the RCx bit in the RCR2 is set, pullup resistors are attached
to the PCx pin. When a pin outputs a low level, the pullup resistor is disconnected regardless of an RCR2
register bit being set
Bits 5–0 have open drain or CMOS output options, which are controlled by the corresponding WOM2
register bits. These open drain or CMOS output options may be selected for either the general-purpose
output ports or the peripheral outputs (EVO, SCK, and SDO).
6.4.1 Port C Data Register
Read
Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output
Write
Anytime; data stored in an internal latch; drives pin only if DDR set for output writes do not change pin
state when pin configured for SDO, SCK, and EVO peripheral output
Reset
Becomes high-impedance input
Address:
$0002
Bit 7
654321
Bit 0
Read:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Write:
Reset:
Unaffected by reset
Figure 6-5. Port C Data Register (PORTC)
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