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參數(shù)資料
| 型號(hào)： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 126/146頁(yè) |
| 文件大?。?/td> | 852K |
| 代理商： | MC68HC05L16CFU |
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Timer System
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
80
Freescale Semiconductor
9.2.3 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch
the value of the free-running counter after the corresponding input capture edge detector senses a
defined transition. The level transition which triggers the counter transfer is defined by the corresponding
input edge bit (IEDG). Reset does not affect the contents of the input capture register.
The result obtained by an input capture will be one more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter, which is four internal bus clock
cycles.
The free-running counter contents are transferred to the input capture register on each proper signal
transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register
always contains the free-running counter value that corresponds to the most recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15)
is also read. This characteristic causes the timer used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they
occur on opposite edges of the internal bus clock.
NOTE
Since the TCAP pin is shared with the PC3 I/O pin, changing the state of
the PC3 DDR or data register can cause an unwanted TCAP interrupt. This
can be handled by clearing the ICIE bit before changing the configuration
of PC3 and clearing any pending interrupts before enabling ICIE.
9.2.4 Timer Control Register
The TCR is a read/write register containing five control bits. Three bits enable interrupts associated with
the timer status register flags ICF, OCF, and TOF.
ICIE — Input Capture Interrupt Enable
0 = Interrupt disabled
1 = Interrupt enabled
OC1IE — Output Compare 1 Interrupt Enable
0 = Interrupt disabled
1 = Interrupt enabled
TOIE — Timer Overflow Interrupt Enable
0 = Interrupt disabled
1 = Interrupt enabled
Address:
$0012
Bit 7
654321
Bit 0
Read:
ICIE
OC1IE
TOIE
0
IEDG
OLVL
Write:
Reset:
000000
U
0
U = Unaffected
Figure 9-3. Timer Control Register (TCR)
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