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| 型號： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 133/146頁 |
| 文件大?。?/td> | 852K |
| 代理商： | MC68HC05L16CFU |
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Timer 2
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
87
9.3.2 Timer Status Register 2
TI2F — Timer Input 2 (EVI) Interrupt Flag
In event mode, the event edge sets TI2F. In gated time accumulation mode, the trailing edge of the
gate signal at the EVI input pin sets TI2F. When the TI2IE bit and this bit are set, an interrupt is
generated. This bit is a read-only bit and writes have no effect. The TI2F is cleared by writing a logic 1
to the RTI2F bit and on reset.
OC2F — Compare 2 Interrupt Flag
The OC2F bit is set when compare match is detected between counter 2 and OC2 register. When
OC2IE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and writes have no
effect. The OC2F is cleared by writing a logic 1 to ROC2F bit and on reset.
Bits 5 and 4 — Reserved
These bits are not used and always read as logic 0.
RTI2F — Reset Timer Input 2 Flag
The RTI2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the TI2F
bit and writing a logic 0 to this bit has no effect.
ROC2F — Reset Output Compare 2 Flag
The ROC2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the OC2F
bit and writing a logic 0 to this bit has no effect.
Bits 1 and 0 — Reserved
These bits are not used and always read as logic 0.
9.3.3 Output Compare Register 2
The OC2 register data is transferred to the buffer register when the CPU writes to TCNT2, when the
CMP2 presets the TCNT2, or when system resets.
When the OC2 buffer register matches the TCNT2 register, the OC2F bit in the TSR2 register is set and
TCNT2 is preset to $01.
Address:
$001D
BIt 7
654321
Bit 0
Read:
TI2F
OC2F
00
Write:
RTI2F
ROC2F
Reset:
00000000
= Unimplemented
Figure 9-9. Timer Status Register 2 (TSR2)
Address:
$001E
BIt 7
654321
Bit 0
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset:
00000000
Figure 9-10. Output Compare Register 2 (OC2)
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