參數(shù)資料
型號： MC68HC05L16CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 82/146頁
文件大?。?/td> 852K
代理商： MC68HC05L16CFU
Resets and Interrupts
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
40
Freescale Semiconductor
4.2 Interrupts
There are six hardware interrupt sources in the MC68HC05L16:
IRQ1 and IRQ2
Key wakeup interrupt (KWI)
Timer 1 (TOI, ICI, and OC1I)
Timer 2 (TI2I and OC2I)
Serial transfer complete interrupt (SSPI)
Timebase interrupt (TBI)
4.2.1 IRQ1 and IRQ2
Two external interrupt request inputs, IRQ1 and IRQ2, share the same vector address at $FFFA and
$FFFB.
Bits IRQ1S and IRQ2S in interrupt control register (INTCR) control whether IRQ1 and IRQ2, respectively,
respond only to the falling edge or falling edge and low level to trigger an interrupt. The IRQ1 and IRQ2
are enabled by IRQ1E and IRQ2E bits and IRQ1F and IRQ2F bits are provided as an indicator in the
interrupt status register (INTSR). Since the IRQ1(2)F can be set by either the pins or the data latches of
PC7(6), be sure to clear the flags by software before setting the IRQ1(2)E bit.
The IRQ1 and the IRQ2 pins are shared with port C bit 7 and bit 6, respectively, and IRQx pin states can
be determined by reading port C pins. The BIL and BIH instructions apply only to the IRQ1 input.
4.2.2 Key Wakeup Interrupt (KWI)
Eight key wakeup inputs (KWI0–KWI7) share pins with port B. Each key wakeup input is enabled by the
corresponding bit in the KWIEN register which resides in the option map, and KWI is enabled by the KWIE
bit in the INTCR. When a falling edge is detected at one of the enabled key wakeup inputs, the KWIF bit
in the INTSR is set and KWI is generated if KWIE = 1. Each input has a latch which responds only to the
falling edge at the pin, and all input latches are cleared at the same time by clearing the KWIF bit. See
4.2.3 IRQ (KWI) Software Consideration
IRQ and KWI interrupts have a timing delay in a case described in Figure 4-2. This section shows
programming for proper interrupts with IRQ or KWI.
Figure 4-1 shows an example of timer1 interrupt. In this case, the interrupt by TOF occurs as soon as the
TOIE (timer1 overflow interrupt enable) bit is set.
Figure 4-1. Timer 1 Interrupt
CLI
BSET TOIE, TCR
LDA
#$55
.
TOF Interrupt pending
Interrupt occurs before this instruction
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