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參數(shù)資料
| 型號： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 116/146頁 |
| 文件大?。?/td> | 852K |
| 代理商： | MC68HC05L16CFU |
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Signal Descriptions
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
71
8.4.1 Control
This block is an interface to the HC05 internal bus and generates a start signal when a write to the SPDR
is detected in master mode. It also generates an interrupt request to the CPU.
8.4.2 SPDR
This serial peripheral data register (SPDR) is an 8-bit shift register. The DORD bit in the SPCR determines
the bus connection between the internal data bus and SPDR. This register can be read and written by the
CPU.
8.4.3 SPCR
Bits in the serial peripheral control register (SPCR) control SSPI functions.
8.4.4 SPSR
The serial peripheral status register (SPSR) mainly sets flags such as SPIF and DCOL.
8.4.5 CLKGEN
In master mode, this block generates SCK when the CPU writes to the data register (SPDR) and the clock
rate is selected by the SPR bit in the control register.
In slave mode, the external clock from the SCK pin is used instead of the master mode clock, and SPR
has no affect.
This clock generator includes a 3-bit clock counter. Overflow of this counter sets SPIF.
8.5 Signal Descriptions
Three basic signals — SDI, SDO, and SCK — are described in the following subsections. The relationship
among SCK, SDI, and SDO is shown in Figure 8-3.
8.5.1 SSPI Data I/O (SDI and SDO)
The two serial data lines — SDI for input and SDO for output — are connected to PC0 and PC1,
respectively, when SSPI is enabled (SPE = 1).
At the falling edge of SCK, a serial data bit is transmitted out of the SDO pin. At the rising edge of SCK,
a serial data bit on the SDI pin is sampled internally.
When data is transmitted to other devices via the SDO line, the receiving data is shifted into the shift
register through the SDI pin. This implies full- duplex transmission with both data-out and data-in
synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receiver-full status bits. A single status bit, SPIF, is
used to signify the completion of data transfer.
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