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| 型號： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 80/146頁 |
| 文件大?。?/td> | 852K |
| 代理商： | MC68HC05L16CFU |
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MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
39
Chapter 4
Resets and Interrupts
4.1 Introduction
In user operating modes, the reset/interrupt vectors are located at the top of the address space
($FFF0–$FFFF). In self-check mode, the reset/interrupt vectors are located at $FFE0–$FFEF in the
internal self-check ROM. Descriptions in this section assume a user operating mode is in use. Table 4-1
shows the address assignments for the vectors.
Upon reset, the I bit in the condition code register is set and interrupts are disabled (masked). When an
interrupt occurs, the I bit is set automatically by hardware after stacking the condition code register (CCR).
All interrupts in the MC68HC05L16 follow a fixed hardware priority circuit to resolve simultaneous
requests.
Each interrupt has a software programmable interrupt mask bit which may be used to selectively inhibit
automatic hardware response. In addition, the I bit in the CCR acts as a class inhibit mask to inhibit all
sources in the I-bit class. RESET and software interrupt (SWI) are not masked by the I bit in the CCR.
SWI is an instruction rather than a prioritized asynchronous interrupt source. In a sense, it is lower in
priority than any source because once any interrupt sequence has begun, SWI cannot override it. In
another sense, it is higher in priority than any hardware sources, except reset, because once the SWI
opcode is fetched, no other sources can be honored until after the first instruction in the SWI service
routine has been executed. SWI causes the I mask bit in the CCR to be set.
Table 4-1. Interrupt Vector Assignments
Vector
Address
Interrupt Source
Masked
by
Local
Mask
Priority
(1 = Highest)
FFF0–FFF1
Timebase
I Bit
TBIE
7
FFF2–FFF3
SSPI
I Bit
SPIE
6
FFF4–FFF5
Timer 2
TI2I
OC2I
I Bit
TI2IE
OC2IE
5
FFF6–FFF7
Timer 1
ICI
OC1I
TOI
I Bit
ICIE
OC1IE
TOIE
4
FFF8–FFF9
KWI
I Bit
KWIE
3
FFFA–FFFB
IRQ
IRQ1
IRQ2
I Bit
IRQ1E
IRQ2E
2
FFFC–FFFD
SWI
None
Same Level as
an Instruction
FFFE–FFFF
Reset
COP
RESET Pin
Power-On
None
COPE
None
1
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