參數(shù)資料
型號： MC68HC05L16CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 106/146頁
文件大?。?/td> 852K
代理商： MC68HC05L16CFU
Oscillators/Clock Distributions
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
62
Freescale Semiconductor
7.4.2.2 XOSC with FOSCE = 0
If XOSC is the system clock, clearing FOSCE will stop OSC and preset the 7-bit divider and 6-bit POR
counter to $0078. Execution will continue with XOSC and when FOSCE is set again, OSC will re-start.
When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the
system clock. The stabilization time will be 8072 counts.
7.4.2.3 XOSC with FOSCE = 0 and STOP
If XOSC is the system clock and FOSCE is cleared, further power reduction can be achieved by executing
the STOP instruction. In this case, OSC is stopped, the 7-bit divider and 6-bit POR counter are preset to
$0078 (since FOSCE = 0) and execution is halted. Exiting STOP with external IRQ does not re-start the
OSC; however, execution begins immediately using XOSC. OSC may be re-started by setting FOSCE.
When the POR counter overflows, FTUP will be set, signaling that OSC is stable and can be used as the
system clock. The stabilization time will be 8072 counts.
7.4.2.4 Stop Mode and Wait Mode
During stop mode, the main oscillator (OSC) is shut down and the clock path from the second oscillator
(XOSC) is disconnected. All modules except timebase are halted. Entering stop mode clears the FTUP
flag in the MISC register and initializes the POR counter. Stop mode is exited by RESET, IRQ1, IRQ2,
KWI, SSPI (slave mode), or timebase interrupt.
If OSC is selected as the system clock source during stop mode, CPU resumes after the overflow of the
POR counter and this overflow also sets the FTUP status flag.
If XOSC is selected as the system clock source during stop mode, no stop recovery time is required for
exiting stop mode because XOSC never stops. Re-start of the main oscillator depends on the FOSCE bit.
During wait mode, only the CPU clocks are halted and the peripheral modules are not affected. Wait mode
is exited by RESET and any interrupts.
Table 7-2. Recovery Time Requirements
Before Reset or Interrupt
Power-On
Reset
External
Reset
Exit Stop
Mode by
Interrupt
CPU Clock Source
Stop
FOSCE
——
—
Wait
—
OSC (OSC on)
Out
1
—
No wait
—
OSC (OSC off)
Out
In
In(1)
1. This case never occurs.
0(2)
1
0(1)
2. This case has no meaning for the applications.
—
Wait
—
Wait
XOSC (OSC on)
Out
1
—
No wait
—
XOSC (OSC off)
Out
In
0
1
0
—
Wait
—
No wait
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