參數(shù)資料
型號: MC68CK338CPV14
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144
封裝: PLASTIC, TQFP-144
文件頁數(shù): 50/133頁
文件大?。?/td> 944K
代理商: MC68CK338CPV14
MC68CK338
MOTOROLA
MC68CK338TS/D
23
SWP — Software Watchdog Prescaler
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. Table 9 gives the
ratio for each combination of SWP and SWT bits.
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor Enable
0 = Disable bus monitor function for internal to external bus cycles.
1 = Enable bus monitor function for internal to external bus cycles.
BMT[1:0] — Bus Monitor Timing
This bit field selects the time-out period in system clocks for the bus monitor. Refer to Table 10.
3.4.2 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge (IACK) cycles.
The monitor asserts BERR if the response time exceeds a user-specified time-out period.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT[1:0] field.
Table 9 Software Watchdog Timing Field
SWP
SWT[1:0]
Watchdog Time-Out Period
000
29
÷ f
sys
001
211
÷ f
sys
010
213
÷ f
sys
011
215
÷ f
sys
100
218
÷ f
sys
101
220
÷ f
sys
110
222
÷ f
sys
111
224
÷ f
sys
Table 10 Bus Monitor Time-Out Period
BMT[1:0]
Bus Monitor Time-Out Period
00
64 system clocks
01
32 system clocks
10
16 system clocks
11
8 system clocks
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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