參數(shù)資料
型號(hào)： MC68CK338CPV14
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 122/133頁(yè)
文件大?。?/td> 944K
代理商： MC68CK338CPV14
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MC68CK338
MOTOROLA
MC68CK338TS/D
89
IL[2:0] — Interrupt Level
Setting IL[2:0] to a non-zero value causes the FCSM to request an interrupt of the selected level when
the COF bit sets. If IL[2:0] = %000, no interrupt will be requested when COF sets. These bits can be
read or written at any time and are cleared by reset.
IARB3 — Interrupt Arbitration Bit 3
This bit works in conjunction with IARB[2:0] in the BIUMCR. Each module that generates interrupt re-
quests on the IMB must have a unique value in the arbitration field. This interrupt arbitration identifica-
tion number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same
priority. The IARB3 bit is cleared by reset. Refer to 6.4.1 BIUSM Registers for more information on
IARB[2:0].
DRV[A:B] — Drive Time Base Bus
This bit field contains read/write bits that control the connection of the FCSM to the time base buses A
and B. These bits are cleared by reset. Refer to Table 52.
WARNING
Two time base buses should not be driven at the same time.
IN — Input Pin Status Bit
This read-only status bit reflects the logic state of the FCSM input pin. Writing to this bit has no effect,
nor does reset.
NOTE
The clock input of FCSM3 is internally connected to I/O pin CTD27 of DASM27 and
will read the state of that pin.
CLK[2:0] — Counter Clock Select
These read/write control bits select one of six internal clock signals (PCLK[1:6]) or one of two external
conditions on the external clock input pin. Maximum frequency of the external clock signals is fsys/4.
Refer to Table 54.
Table 50 Drive Time Base Bus Field
DRVA
DRVB
Bus Selected
0
No time base bus driven
0
1
Time base bus B is driven
1
0
Time base bus A is driven
1
Both time base buses A and B are driven
Table 51 Counter Clock Select Field
CLK2
CLK1
CLK0
Free-Running Counter Clock Source
000
PCLK1 (fsys ÷ 2 or fsys ÷ 3)
001
PCLK2 (fsys ÷ 4 or fsys ÷ 6)
010
PCLK3 (fsys ÷ 8 or fsys ÷ 12)
011
PCLK4 (fsys ÷ 16 or fsys ÷ 24)
100
PCLK5 (fsys ÷ 32 or fsys ÷ 48)
101
PCLK6 (fsys ÷ 64 or fsys ÷ 768)
1
0
External clock input, falling edge
1
External clock input, rising edge
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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