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| 型號(hào)： | MC68CK338CPV14 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 11/133頁(yè) |
| 文件大?。?/td> | 944K |
| 代理商： | MC68CK338CPV14 |
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MOTOROLA
MC68CK338
108
MC68CK338TS/D
6.12.1 PIOSM Register
The PIOSM control register is composed of two 8-bit registers. The upper eight bits contain the data
register and the lower eight bits contain the data direction register. Each PIOSM pin may be pro-
grammed as an input or an output under software control. The data direction register controls whether
the corresponding pins are inputs or outputs.
The PIOSM data register can be read or written by the processor. For pins programmed as outputs, a
read of the data register actually reads the value of the output data latch and not the I/O pin.
CTIO[7:6] are not bonded to pins on the MC68338. When one of these signals is configured as an input,
a read of the corresponding data bit always returns a zero. When one of these signals is configured as
an output, a read of the corresponding data bit returns the value stored in the output data latch.
NOTE
Care should be taken when a single word write cycle is used to modify the data reg-
ister and data direction register of the PIOSM. Undesired glitches can occur on pins
that change from inputs to outputs and vice versa. To avoid this, first use a byte
write cycle to modify the data register then use another byte write cycle to modify
the data direction register.
6.13 Static RAM Submodule (RAMSM)
The static RAM submodule (RAMSM) provides 32 bytes (16 words) of contiguous memory locations
and is not relocatable. It is especially useful for storage of variables and system parameters that must
be maintained when the rest of the MCU is powered down. Data can be read or written in bytes, words,
or long words. RAMSM locations are not affected by reset.
The CTM6 has two RAMSMs. Table 65 shows the RAMSM address locations.
6.14 RTCSM and RAMSM Standby Operation
The standby power switch in CTM6 monitors VDD and selects either VDD and VDDSYN or VRTC for the
power source of the RTCSM and RAMSMs, depending on the level of VDD.
When VDD is within the specified operating range, the RTCSM low-power oscillator is powered by
VDDSYN and the RAMSMs are powered by VDD. VDD also provides power to the digital logic portion of
the RTCSM, therefore both VDD and VDDSYN must be kept equal to each other for normal operation.
When VDD and VDDSYN are powered down, the submodules are powered by VRTC and are in standby
mode. In standby mode, the RTCSM continues to keep time if enabled. However, updates to the 15-bit
prescaler and 32-bit free-running counter buffer registers are halted in order to conserve power. All
PIO17A — PIOSM Control Register
$YFF488
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DDR7
DDR6
DDR5
DDR4
DDR3
DDR2
DDR1
DDR0
RESET:
0
U
0
Table 65 RAMSM Address Locations
Static RAM Submodule
Address
32
$YFF500–51E
36
$YFF520–53E
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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