參數(shù)資料
型號： MC68CK338CPV14
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144
封裝： PLASTIC, TQFP-144
文件頁數(shù)： 129/133頁
文件大?。?/td> 944K
代理商： MC68CK338CPV14
MC68CK338
MOTOROLA
MC68CK338TS/D
95
SICA and SICB contain the control and status bits for SASM channels A and B, respectively. SICA also
contains the IL[2:0] interrupt level field and IARB3 interrupt arbitration bit 3 for both SASM channels A
and B.
FLAG — Event Flag
FLAG indicates whether or not an input capture or output compare event has occurred. If the IL[2:0]
field is non-zero, and IEN is set, an interrupt request is generated when FLAG is set.
0 = An input capture or output compare event has not occurred
1 = An input capture or output compare event has occurred
Table 56 shows the event flag status during different modes.
FLAG is set only by hardware and cleared only by software or by a system reset.To clear this bit, first
read the register with FLAG set to one, then write a zero to the bit.
NOTE
The flag clearing mechanism works only if no flag setting event occurs between the
read and write operations. If a FLAG setting event occurs between the read and
write operations, the FLAG bit will not cleared.
IL[2:0] — Interrupt Level
Setting IP[2:0] to a non-zero value causes the SASM to request an interrupt when the FLAG bit sets. If
IL[2:0] = %000, no interrupts will be requested when FLAG sets.
NOTE
This field affects both SASM channels, not just channel A.
IARB3 — Interrupt Arbitration Bit 3
This bit works in conjunction with IARB[2:0] in the BIUMCR. Each module that generates interrupt re-
quests on the IMB must have a unique value in the arbitration field. This interrupt arbitration identifica-
tion number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same
priority. The IARB3 bit is cleared by reset. Refer to 6.4.1 BIUSM Registers for more information on
IARB[2:0].
SIC12B, SIC14B — SASM Status/Interrupt/Control Register B
$YFF464, $YFF474
SIC18B, SIC24B — SASM Status/Interrupt/Control Register B
$YFF494, $YFF4C4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FLAG
0
IEN
0
BSL
IN
0
FORCE EDOUT
0
MODE[1:0]
RESET:
0
U
0
Table 56 Event Flag Status Conditions
Mode
Status Description
IC
If a subsequent input capture event occurs while FLAG is set, the new value is latched and
FLAG remains set.
OC
If a subsequent output compare event occurs while FLAG is set, the compare occurs normally
and FLAG remains set.
OCT
If a subsequent output compare event occurs while FLAG is set, the output signal toggles nor-
mally and FLAG remains set.
OP
If a subsequent internal compare event occurs while FLAG is set, the compare occurs normally
and FLAG remains set.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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