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| 型號(hào)： | MC68CK338CPV14 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 3/133頁 |
| 文件大?。?/td> | 944K |
| 代理商： | MC68CK338CPV14 |
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MOTOROLA
MC68CK338
100
MC68CK338TS/D
FLAG — Event Flag
This status bit indicates whether or not an input capture or output compare event has occurred. If the
IL[2:0] field is non-zero, an interrupt request is generated when FLAG is set.
0 = An input capture or output compare event has not occurred
1 = An input capture or output compare event has occurred
Table 56 shows the event flag status during different modes.
FLAG is set only by hardware and cleared by software or by a system reset. To clear the bit, first read
the register with FLAG set to one, then write a zero to the bit. Placing the DASM in DIS mode will also
clear the flag.
NOTE
The flag clearing mechanism works only if no flag setting event occurs between the
read and write operations. If a FLAG setting event occurs between the read and
write operations, the FLAG bit will not be cleared.
IL[2:0] — Interrupt Level
Setting IL[2:0] to a non-zero value causes the DASM to request an interrupt when the FLAG bit sets. If
IL[2:0] = %000, no interrupt will be requested when FLAG sets.
IARB3 — Interrupt Arbitration Bit 3
This bit works in conjunction with IARB[2:0] in the BIUMCR. Each module that generates interrupt re-
quests on the IMB must have a unique value in the arbitration field. This interrupt arbitration identifica-
tion number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same
priority. The IARB3 bit is cleared by reset. Refer to 6.4.1 BIUSM Registers for more information on
IARB[2:0].
WOR — Wired-OR Mode
In the DIS, IPWM, IPM and IC modes, WOR is not used. Reading this bit returns the value that was
previously written.
In the OCB, OCAB and OPWM modes, WOR selects whether the output buffer is configured for normal
or open drain operation.
0 = Output buffer operates in normal mode
1 = Output buffer operates in open drain mode
BSL — Bus Select
This bit selects the time base bus connected to the DASM.
0 = DASM is connected to time base bus A.
1 = DASM is connected to time base bus B.
Table 60 Event Flag Status Conditions
Mode
Status Description
DIS
FLAG bit is cleared
IPWM
FLAG bit is set each time there is a capture on channel A
IPM
FLAG bit is set each time there is a capture on channel A, except for the first time
IC
FLAG bit is set each time there is a capture on channel A
OCB
FLAG bit is set each time there is a successful comparison on channel B
OCAB
FLAG bit is set each time there is a successful comparison on either channel A or B
OPWM
FLAG bit is set each time there is a successful comparison on channel A
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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