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| 型號(hào)： | MC68CK338CPV14 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 130/133頁(yè) |
| 文件大?。?/td> | 944K |
| 代理商： | MC68CK338CPV14 |
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MOTOROLA
MC68CK338
96
MC68CK338TS/D
NOTE
This bit field affects both SASM channels, not just channel A.
IEN — Interrupt Enable
This control bit enables interrupts when FLAG is set and the IL[2:0] field is non-zero.
0 = Interrupts disabled
1 = Interrupts enabled
BSL — Time Base Bus Select
This control bit selects the time base bus connected to the SASM.
0 = Time base bus A selected
1 = Time base bus B selected
IN — Input Pin Status
In input mode (IC), the IN bit reflects the logic state present on the corresponding input pin after being
Schmitt triggered and synchronized.
In the output modes (OC, OCT and OP), the IN bit value reflects the state of the output flip-flop.
The IN bit is a read-only bit. Reset has no effect on this bit.
NOTE
The input of SASM12A is internally connected to I/O pin CTD29 and will read the
state of that pin. The input of SASM12B is internally connected to I/O pin CTD26
and will read the state of that pin.
FORCE — Force Compare Control
In the IC and OP modes, FORCE is not used and writing to it has no effect.
In the OC and OCT modes, FORCE is used by software to cause the output flip-flop (and the output
pin) to behave as though an output compare had occurred. In OC and OCT mode, setting FORCE caus-
es the value of EDOUT to be transferred to the output of the output flip-flop. Internal synchronization
ensures that the correct level appears on the output pin when a new value is written to EDOUT and
FORCE is set at the same time.
0 = No action
1 = Force output flip-flop to behave as if an output compare has occurred
FORCE is cleared by reset and always reads as zero.
NOTE
FLAG is not affected by the use of the FORCE bit.
EDOUT — Edge Detect and Output Level
In IC mode, EDOUT is used to select the edge that triggers the input capture circuitry.
0 = Input capture on falling edge
1 = Input capture on rising edge
In OC and OCT mode, the EDOUT bit is used to latch the value to be output to the pin on the next output
compare match or when the FORCE is set. Internal synchronization ensures that the correct level ap-
pears on the output pin when a new value is written to EDOUT and FORCE is set at the same time.
Reading EDOUT returns the previous value written.
In OP mode, the value of EDOUT is output to the corresponding pin. Reading EDOUT returns the pre-
vious value written.
MODE[1:0] — SASM Operating Mode
This bit field selects the mode of operation for the SASM channel. Refer to Table 57.
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