參數(shù)資料
型號(hào): MC68711E20VFNE2
廠商: Freescale Semiconductor
文件頁數(shù): 85/138頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 52-PLCC
標(biāo)準(zhǔn)包裝: 23
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 4MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 38
程序存儲(chǔ)器容量: 20KB(20K x 8)
程序存儲(chǔ)器類型: OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 52-LCC(J 形引線)
包裝: 管件
Resets, Interrupts, and Low-Power Modes
MC68HC711D3 Data Sheet, Rev. 2.1
50
Freescale Semiconductor
Table 4-2 provides a list of the interrupts with a vector location in memory for each, as well as the actual
condition code and control bits that mask each interrupt. Figure 4-3 shows the interrupt stacking order.
Table 4-2. Interrupt and Reset Vector Assignments
Vector
Address
Interrupt Source
CCR
Mask
Local
Mask
$FFC0, $FFC1
$FFD4, $FFD5
Reserved
$FFD6, $FFD7
SCI serial system:
SCI transmit complete
SCI transmit data register empty
SCI idle line detect
SCI receiver overrun
SCI receive data register full
I bit
TCIE
TIE
ILIE
RIE
$FFD8, $FFD9
SPI serial transfer complete
I bit
SPIE
$FFDA, $FFDB
Pulse accumulator input edge
I bit
PAII
$FFDC, $FFDD
Pulse accumulator overflow
I bit
PAOVI
$FFDE, $FFDF
Timer overflow
I bit
TOI
$FFE0, $FFE1
Timer input capture 4/output compare 5
I bit
I4/O5I
$FFE2, $FFE3
Timer output compare 4
I bit
OC4I
$FFE4, $FFE5
Timer output compare 3
I bit
OC3I
$FFE6, $FFE7
Timer output compare 2
I bit
OC2I
$FFE8, $FFE9
Timer output compare 1
I bit
OC1I
$FFEA, $FFEB
Timer input capture 3
I bit
IC3I
$FFEC, $FFED
Timer input capture 2
I bit
IC2I
$FFEE, $FFEF
Timer input capture 1
I bit
IC1I
$FFF0, $FFF1
Real time interrupt
I bit
RTII
$FFF2, $FFF3
IRQ (external pin)
I bit
None
$FFF4, $FFF5
XIRQ pin (pseudo non-maskable)
X bit
None
$FFF6, $FFF7
Software interrupt
None
$FFF8, $FFF9
Illegal opcode trap
None
$FFFA, $FFFB
COP failure (reset)
None
NOCOP
$FFFC, $FFFD
Clock monitor fail (reset)
None
CME
$FFFE, $FFFF
RESET
None
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