參數(shù)資料
型號(hào)： MC68EC030FE25CB1
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 1/36頁(yè)
文件大小： 0K
描述： IC MPU 32BIT ENH 25MHZ 132-CQFP
標(biāo)準(zhǔn)包裝： 180
系列： M680x0
處理器類型： M680x0 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 132-BCQFP
供應(yīng)商設(shè)備封裝： 132-CQFP（24x24）
包裝： 托盤
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MOTOROLA
Technical Summary
Second-Generation 32-Bit Enhanced Embedded
Controller
The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for
the requirements of embedded control applications. The MC68EC030 is optimized to maintain
performance while using cost-effective memory subsystems. The rich instruction set and addressing
mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear
migration path for M68000 systems. The main features of the MC68EC030 are as follows:
Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors
Burst-Mode Bus Interface for Efficient DRAM Access
On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)
Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices
25- and 40-MHz Operating Frequency (up to 9.2 MIPS)
Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications
Additional features of the MC68EC030 include:
Complete 32-Bit Nonmultiplexed Address and Data Buses
Sixteen 32-Bit General-Purpose Data and Address Registers
Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers
Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection
Pipelined Architecture with Increased Parallelism Allows:
– Internal Caches Accesses in Parallel with Bus Transfers
– Overlapped Instruction Execution
Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)
Complete Support for Coprocessors with the M68000 Coprocessor Interface
Internal Status Indication for Hardware Emulation Support
4-Gbyte Direct Addressing Range
Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density
NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size
MC68EC030
Order this document
by MC68EC030/D
Rev. 1
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA INC., 1991
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68EC030FE40B 制造商:Motorola Inc 功能描述:
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MC68EC030FE40C 制造商:Freescale Semiconductor 功能描述:Microprocessor
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