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參數(shù)資料
| 型號： | MC68711E20VFNE2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 70/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 52-PLCC |
| 標準包裝： | 23 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 20KB（20K x 8） |
| 程序存儲器類型： | OTP |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 52-LCC（J 形引線） |
| 包裝： | 管件 |
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Data Types
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
37
3.2.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1).
Otherwise, the N bit is cleared. A result is said to be negative if its most significant bit (MSB) is a 1. A quick
way to test whether the contents of a memory location has the MSB set is to load it into an accumulator
and then check the status of the N bit.
3.2.6.5 I-Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable interrupt sources.
While the I bit is set, interrupts can become pending, but the operation of the CPU continues uninterrupted
until the I bit is cleared. After any reset, the I bit is set by default and can be cleared only by a software
instruction. When an interrupt is recognized, the I bit is set after the registers are stacked, but before the
interrupt vector is fetched. After the interrupt has been serviced, a return-from-interrupt instruction is
normally executed, restoring the registers to the values that were present before the interrupt occurred.
Normally, the I bit is 0 after a return from interrupt is executed. Although the I bit can be cleared within an
interrupt service routine, "nesting" interrupts in this way should be done only when there is a clear
understanding of latency and of the arbitration mechanism. Refer to Chapter 4 Resets, Interrupts, and
3.2.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an ADD, ABA,
or ADC instruction. Otherwise, the H bit is cleared. Half carry is used during BCD operations.
3.2.6.7 X-Interrupt Mask (X)
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set by default and must
be cleared by a software instruction. When an XIRQ interrupt is recognized, the X and I bits are set after
the registers are stacked, but before the interrupt vector is fetched. After the interrupt has been serviced,
an RTI instruction is normally executed, causing the registers to be restored to the values that were
present before the interrupt occurred. The X interrupt mask bit is set only by hardware (RESET or XIRQ
acknowledge). X is cleared only by program instruction (TAP, where the associated bit of A is 0; or RTI,
where bit 6 of the value loaded into the CCR from the stack has been cleared). There is no hardware
action for clearing X.
3.2.6.8 STOP Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from putting the M68HC11 into a
low-power stop condition. If the STOP instruction is encountered by the CPU while the S bit is set, it is
treated as a no-operation (NOP) instruction, and processing continues to the next instruction. S is set by
reset; STOP is disabled by default.
3.3 Data Types
The M68HC11 CPU supports four data types:
1.
Bit data
2.
8-bit and 16-bit signed and unsigned integers
3.
16-bit unsigned fractions
4.
16-bit addresses
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