參數(shù)資料
型號： MC68711E20VFNE2
廠商： Freescale Semiconductor
文件頁數(shù)： 72/138頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 52-PLCC
標(biāo)準包裝： 23
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 38
程序存儲器容量： 20KB（20K x 8）
程序存儲器類型： OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 52-LCC（J 形引線）
包裝： 管件
Instruction Set
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
39
3.5.3 Extended
In the extended addressing mode, the effective address of the argument is contained in two bytes
following the opcode byte. These are 3-byte instructions (or 4-byte instructions if a prebyte is required).
One or two bytes are needed for the opcode and two for the effective address.
3.5.4 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in an index register (IX or IY). The sum is the effective address. This addressing mode allows
referencing any memory location in the 64-Kbyte address space. These are 2- to 5-byte instructions,
depending on whether a prebyte is required.
3.5.5 Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is contained in
the opcode. Operations that use only the index registers or accumulators, as well as control instructions
with no arguments, are included in this addressing mode. These are 1- or 2-byte instructions.
3.5.6 Relative
The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit
signed offset included in the instruction is added to the contents of the program counter to form the
effective branch address. Otherwise, control proceeds to the next instruction. These are usually 2-byte
instructions.
3.6 Instruction Set
Refer to Table 3-2, which shows all the M68HC11 instructions in all possible addressing modes. For each
instruction, the table shows the operand construction, the number of machine code bytes, and execution
time in CPU E-clock cycles.
Table 3-2. Instruction Set (Sheet 1 of 8)
Mnemonic
Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
X
H
I
N
Z
V
C
ABA
Add
Accumulators
A + B
AINH
1B
—
2
—
—
ABX
Add B to X
IX + (00 : B)
IX
INH
3A
—
3
—
——
———
——
ABY
Add B to Y
IY + (00 : B)
IY
INH
18
3A
—
4
—
——
———
——
ADCA (opr)
Add with Carry
to A
A + M + C
AA
IMM
ADIR
AEXT
AIND,X
AIND,Y
89
99
B9
A9
18
A9
ii
dd
hh
ll
ff
2
3
4
5
——
—
ADCB (opr)
Add with Carry
to B
B + M + C
BB
IMM
BDIR
BEXT
BIND,X
BIND,Y
C9
D9
F9
E9
18
E9
ii
dd
hh
ll
ff
2
3
4
5
——
—
ADDA (opr)
Add Memory to
A
A + M
A
A
IMM
ADIR
AEXT
AIND,X
AIND,Y
8B
9B
BB
AB
18
AB
ii
dd
hh
ll
ff
2
3
4
5
——
—
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