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| 型號： | MC68711E20VFNE2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 49/138頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 52-PLCC |
| 標(biāo)準(zhǔn)包裝： | 23 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 20KB（20K x 8） |
| 程序存儲器類型： | OTP |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 52-LCC（J 形引線） |
| 包裝： | 管件 |
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General Description
MC68HC711D3 Data Sheet, Rev. 2.1
18
Freescale Semiconductor
1.10 Non-Maskable Interrupt/Programming Voltage (XIRQ/VPP)
The XIRQ input provides the capability for asynchronously applying non-maskable interrupts to the MCU
after a power-on reset (POR). During reset, the X bit in the condition code register (CCR) is set masking
any interrupt until enabled by software. This level-sensitive input requires an external pullup resistor to
VDD.
In the programming configuration of the bootstrap mode, this pin is used to supply one-time
programmable read-only memory (OTPROM) programming voltage, VPP, to the MCU. To avoid
programming accidents during reset, this pin should be equal to VDD during normal operation unless
XIRQ is active.
1.11 MODA and MODB (MODA/LIR and MODB/VSTBY)
As reset transitions, these pins are used to latch the part into one of the four central processor unit (CPU)
controlled modes of operation. The LIR output can be used as an aid to debugging once reset is
completed. The open-drain LIR pin goes to an active low during the first E-clock cycle of each instruction
and remains low for the duration of that cycle. The VSTBY input is used to retain random-access memory
(RAM) contents during power down.
1.12 Read/Write (R/W)
This pin performs either of two separate functions, depending on the operating mode.
In single-chip and bootstrap modes, R/W functions as input/output port D bit 7. Refer to Chapter 5
Input/Output (I/O) Ports for further information.
In expanded multiplexed and test modes, R/W performs a read/write function. R/W controls the
direction of transfers on the external data bus.
1.13 Port D Bit 6/Address Strobe (PD6/AS)
This pin performs either of two separate functions, depending on the operating mode.
In single-chip and bootstrap modes, the pin functions as input/output port D bit 6.
In the expanded multiplexed and test modes, it provides an address strobe (AS) function. AS is
used to demultiplex the address and data signals at port C.
Refer to Chapter 2 Operating Modes and Memory for further information.
1.14 Input/Output Lines (PA7–PA0, PB7–PB0, PC7–PC0, and PD7–PD0)
In the 44-pin PLCC package, 32 input/output lines are arranged into four 8-bit ports: A, B, C, and D. The
lines of ports B, C, and D are fully bidirectional. Port A has two bidirectional, three input-only, and three
output-only lines in the 44-pin PLCC packaging. In the 40-pin DIP, two of the output-only lines are not
bonded.
Each of these four ports serves a purpose other than input/output (I/O), depending on the operating mode
or peripheral functions selected.
NOTE
Ports B, C, and two bits of port D are available for I/O functions only in
single-chip and bootstrap modes.
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