參數(shù)資料
型號(hào)： MB814405C-60
廠商： Fujitsu Limited
英文描述： CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 100萬(wàn)× 4位超頁(yè)模式動(dòng)態(tài)RAM的CMOS（100萬(wàn)× 4位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 27/30頁(yè)
文件大小： 372K
代理商： MB814405C-60
27
MB814405C-60/MB814405C-70
HIGH-Z
“H” or “L”
DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is
operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of t
RASS
(more than 100
μ
s),
the device can be entered the self refresh cycle. And after that, refresh operation is automatically executed per fixed interval using
internal refresh address counter during “RAS=L” and “CAS=L”.
And exit from self refresh cycle is performed by toggling of RAS and CAS to “H” with specifying t
CHS
min.
Restruction for Self refresh operation ;
For self refresh operation, the notice below must be considered.
1) In the case that distribute CBR refresh are operated in read/write cycles
Self refresh cycles can be executed without special rule if 1024 cycles of distribute CBR refresh are executed within t
REF
max..
2) In the case that burst CBR refresh or RAS-only refresh are operated in read/write cycles
1024 times of burst CBR refresh or 1024 times of burst RAS-only refresh must be executed before and after Self refresh
cycles.
Fig. 21 – SELF REFRESH CYCLE (A
0
- A
9
= OE = “H” or “L”)
RAS
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
CAS
WE
D
OUT
(At recommended operating conditions unless otherwise noted.)
Note: Assumes set refresh cycle only
t
OH
t
CPN
t
RASS
Parameter
Unit
Min.
100
Max.
No.
Min.
100
Max.
100
—
Symbol
101
119
—
—
104
102
–50
–50
—
—
—
μ
s
ns
ns
RAS Pulse Width
RAS Precharge Time
CAS Hold Time
MB814405C-60
MB814405C-70
t
RASS
t
RPS
t
CHS
t
CSR
t
WSR
t
WHR
t
CHS
t
RPC
t
RPS
t
OFF
1024 times of burst refresh
Read/Write operation
t
SN
< 1ms
1024 times of burst refresh
Self Refresh operation
t
RASS
Read/Write operation
RAS
V
IH
V
IL
t
NS
< 1ms
相關(guān)PDF資料
PDF描述
MB814405C-70 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60L 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-70 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-7OL 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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MB81461-12PSZ 制造商:FUJITSU 功能描述:VRAM, FAST PAGE, 64KX4, 24 Pin, Plastic, ZIP
MB81461B-12 制造商:FUJITSU 功能描述: 制造商:FUGITSU 功能描述:81461B-12 制造商:FUJITSU 功能描述:81461B-12
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