參數(shù)資料
型號： MB814405C-60
廠商： Fujitsu Limited
英文描述： CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 100萬× 4位超頁模式動態(tài)RAM的CMOS（100萬× 4位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 10/30頁
文件大?。?/td> 372K
代理商： MB814405C-60
10
MB814405C-60/MB814405C-70
Notes: 1. Referenced to V
SS
.
2. I
CC
depends on the output load conditions and cycle rates; The specified values are obtained with the
output open.
I
CC
depends on the number of address change as RAS= V
IL
and CAS= V
IH
I
CC1
, I
CC3
and I
CC5
are specified at one time of address change during RAS= V
IL
and CAS= V
IH
.
I
CC4
is specified at one time of address change during one Page cycle.
3. An Initial pause (RAS=CAS=V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-only
cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum
of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
4. AC characteristics assume t
T
= 2 ns.
5. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Also transition times
are measured between V
IH
(min) and V
IL
(max).
6. Assumes that t
RCD
≤
t
RCD
(max), t
RAD
≤
t
RAD
(max). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown. Refer
to Fig. 2 and 3.
7. If t
RCD
≥
t
RCD
(max), t
RAD
≥
t
RAD
(max), and t
ASC
≥
t
AA
– t
CAC
– t
T
, access time is t
CAC
.
8. If t
RAD
≥
t
RAD
(max) and t
ASC
≤
t
AA
– t
CAC
– t
T
, access time is t
AA
.
9. Measured with a load equivalent to two TTL loads and 100 pF.
10. t
OFF
and t
OEZ
is specified that output buffer change to high impedance state.
11. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. t
RCD
(max) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. t
RCD
(min) = t
RAH
(min)+ 2t
T
+ t
ASC
(min).
13. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. t
RAD
(max) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
15. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min) the data output pin will remain High-Z state
through entire cycle.
16. Assumes that t
WCS
< t
WCS
(min).
17. Either t
DZC
or t
DZO
must be satisfied.
18. t
CPA
is access time from the selection of a new column address (that is caused by changing CAS from
“L” to “H”). Therefore, if t
CP
is long, t
CPA
is longer than t
CPA
(max) as showm in Fig. 4.
19. Assumes that CAS-before-RAS refresh.
20. Assumes that Test mode function.
21. The last CAS rising edge.
22. The first CAS falling edge.
相關(guān)PDF資料
PDF描述
MB814405C-70 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
MB814405D-60 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
MB814405D-60L 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
MB814405D-70 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
MB814405D-7OL 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
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