參數(shù)資料
型號(hào)： MB814405C-60
廠商： Fujitsu Limited
英文描述： CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 100萬(wàn)× 4位超頁(yè)模式動(dòng)態(tài)RAM的CMOS（100萬(wàn)× 4位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 1/30頁(yè)
文件大?。?/td> 372K
代理商： MB814405C-60
DS05-10181-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS 1M
HYPER PAGE MODE DYNAMIC RAM
×
4 BIT
MB814405C-60/-70
CMOS 1,048,576
×
4 BIT Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB814405C is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory cells
accessible in 4-bit increments. The MB814405C features the “hyper page” mode of operation which provides
extended valid time for data output and higher speed random access of up to 1,024
same row than the fast page mode. The MB814405C DRAM is ideally suited for mainframe, buffers, hand-held
computers video imaging equipment, and other memory applications where very low power dissipation and high
bandwidth are basic requirements of the design. Since the standby current of the MB814405C is very small, the
device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power.
The MB814405C is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and
extends the time interval between memory refreshes. Clock timing requirements for the MB814405C are not
critical and all inputs are TTL compatible.
×
4 bits of data within the
I
PRODUCT LINE & FEATURES
Parameter
MB814405C-60
60 ns max.
15 ns max.
30 ns max.
104 ns max.
25 ns min.
336 mW max.
363 mW max.
11 mW max. (TTL level)/5.5 mW max. (CMOS level)
MB814405C-70
70 ns max.
20 ns max.
35 ns max.
119 ns min.
30 ns min.
297 mW max.
303 mW max.
RAS Access Time
CAS Access Time
Address Access Time
Random Cycle Time
Fast Page Mode Cycle Time
Low Power
Dissipation
Operating
current
Normal Mode
Hyper Page Mode
Standby current
1,048,576 words
×
4 bit organization
Silicon gate, CMOS, Advanced-Stacked
Capacitor Cell
All input and output are TTL compatible
1024 refresh cycles every 16.4 ms
Self refresh function
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
Early write or OE controlled write capability
RAS-only, CAS-before-RAS, or Hidden Refresh
Hyper Page Mode, Read-Modify-Write capability
On chip substrate bias generator for high
performance
相關(guān)PDF資料
PDF描述
MB814405C-70 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60L 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-70 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-7OL 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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