參數(shù)資料
型號(hào): MB814405C-60
廠商: Fujitsu Limited
英文描述: CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述: 的CMOS 100萬(wàn)× 4位超頁(yè)模式動(dòng)態(tài)RAM的CMOS(100萬(wàn)× 4位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存)
文件頁(yè)數(shù): 20/30頁(yè)
文件大小: 372K
代理商: MB814405C-60
20
MB814405C-60/MB814405C-70
Fig. 13 – HYPER PAGE MODE DELAYED WRITE CYCLE (OE CONTROLLED)
DESCRIPTION
The hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for
the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the hyper
page mode delayed write cycle, OE must be changed from Low to High before WE goes Low (t
OED
+ t
T
+ t
DS
).
“H” or “L”
Invalid Data
DQ
(Input)
DQ
(Output)
RAS
CAS
WE
A
0
to A
9
OE
VALID
DATA IN
VALID
DATA IN
COL
ADD
COL
ADD
ROW
ADD
HIGH-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
RASP
t
RP
t
CAS
t
CRP
t
CSH
t
RCD
t
HPC
t
CP
t
RSH
t
CAS
t
CWL
t
CAH
t
ASC
t
ASC
t
CAH
t
RAH
t
ASR
t
RWL
t
WCH
t
CWL
t
WCH
t
RCS
t
WP
t
WP
t
DH
t
DH
t
DS
t
DS
t
DZC
t
ON
t
ON
t
OED
t
OED
t
OEH
t
OEZ
t
OEH
t
OEZ
t
ON
t
ON
t
DZO
相關(guān)PDF資料
PDF描述
MB814405C-70 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60L 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-70 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-7OL 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB814405D-60PJN 制造商:FUJITSU Component Ltd 功能描述:
MB8146112 制造商:FUJITSU 功能描述:*
MB81461-12PSZ 制造商:FUJITSU 功能描述:VRAM, FAST PAGE, 64KX4, 24 Pin, Plastic, ZIP
MB81461B-12 制造商:FUJITSU 功能描述: 制造商:FUGITSU 功能描述:81461B-12 制造商:FUJITSU 功能描述:81461B-12
MB81464-12 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:MOS 262,144 BIT DYNAMIC RANDOM ACCESS MEMORY