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參數(shù)資料
| 型號： | MB8116165B-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動(dòng)態(tài)RAM) |
| 中文描述： | 1米× 16位的超頁模式動(dòng)態(tài)RAM的CMOS（1米× 16位超級頁面存取模式動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 575K |
| 代理商： | MB8116165B-60 |
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26
MB8116165B-50/-60
t
CSR
t
RP
t
RCS
t
FCAH
t
ASC
t
CWL
t
RWL
t
WP
t
CHR
t
FRSH
t
FCAS
t
FCWD
t
DH
t
DS
t
DZC
t
OED
t
ON
t
DZO
t
OEZ
t
OEH
VALID DATA IN
COLUMN ADDRESSES
t
FCAC
HIGH-Z
HIGH-Z
t
OEA
t
CP
LCAS,
UCAS
A
0
to A
11
RAS
DQ
(Output)
Fig. 19 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
WE
OE
DQ
(Input)
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function
of CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Addresses: Bits A
0
through A
11
are defined by the on-chip refresh counter.
Column Addresses: Bits A
0
through A
7
are defined by latching levels on A
0
to A
7
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows;
1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 4,096 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-
before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 4,096 times with addresses
generated by the internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 4,096 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
MB8116165B-60
Min
.
—
MB8116165B-50
Min.
—
Unit
Parameter
Max.
50
—
—
—
—
ns
No
.
Max.
45
—
—
—
—
69
70
71
72
73
Symbol
(At recommended operating conditions unless otherwise noted.)
CAS to WE Delay Time
CAS Pulse Width
RAS Hold Time
35
70
50
50
ns
35
63
45
45
Column Address Hold Time
ns
ns
ns
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
Note:
Assumes that CAS-before-RAS refresh counter test cycle only.
Valid Data
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
HIGH-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
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