參數(shù)資料
型號(hào): M5M4V16169DRT-10
廠商: Mitsubishi Electric Corporation
英文描述: 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
中文描述: 16MCDRAM:16米(100萬字由16位)與16K的緩存內(nèi)存(1024字由16位)的SRAM
文件頁數(shù): 57/64頁
文件大?。?/td> 737K
代理商: M5M4V16169DRT-10
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1&Read (WB1->WB2->DRAM->RB) Latency set=1
Buffer Write (DIN->WB1)
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
K
CMd#
2
3
4
5
6
7
8
9
10
11
12
13
14
1
RAS#
CAS#
DTD#
Ad0-2
Ad3-11
WB1
New Data[WB1(0-7)]
Old Data
**Col
CS#
Ad1-Ad2=Low
PCG
BW
DPD DPD
DES
DPD DPD
BW
ACT
BW
DWT1R
PCG
BW
DPD
BW
DNOP
DNOP
DPD DPD DPD
BW
BW
BW
BW
BW
BW
BW
BW
DQ0-15
tRC
tRP
tRCD
Row
Row
tRAS
tRWL
1
2
3
4
5
6
7
0
1
2
3
4
5
DRAM
SRAM
0
WB2
1
2
3
4
5
6
7
0
1
2
3
4
0
RB1
Old Data
New Data[WB1(0-7)]
tCBF
tCBF
Ad0=High
New Data on RB appears as to latency set count. See DRT timing chart.
57
RB2
Old Data
New Data[WB1(0-7)]
tCBF
Latency x t
K
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
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