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參數(shù)資料
| 型號： | M5M4V16169DRT-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 中文描述： | 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM |
| 文件頁數(shù)： | 13/64頁 |
| 文件大?。?/td> | 737K |
| 代理商： | M5M4V16169DRT-10 |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (6)
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
DRAM Write
Transfer1
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-Ad11 must be set to Low. The Mask present in WB1 is
also transferred to WB2 and controls the data written to the DRAM. After data has been
transferred from WB1 to WB2 in the present cycle, the entire WB1 Mask is Set. (Notes 3,4)
DRAM Write
Transfer1
& Read
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-A11 must be set to Low. The transfer mask present in
WB1 is also transferred to WB2 and controls the data written to the DRAM. The block to which
the data is written in DRAM is simultaneously transferred to the Read Buffer.(Notes 2,3,4)
13
X
SRAM
1KX16
SRAM RowDecoder
8X16
8X16
8X16
8X16
8X16
16bits
16bits
16bits
As3-9
1of128Decode
DRAM
1M X 16
Ad0-11
1of4096Decode
Ad3-7
1of32
Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
Upper Byte
Lower Byte
Upper Byte
Lower Byte
DRAM RowDecoder
16bits
As0-2
1of8Decode
Lower Byte
RB2
Upper Byte
Lower Byte
RB1
DQs
SRAM
1KX16
8X16
8X16
8X16
8X16
8X16
16bits
16bits
16bits
As3-9
1of128Decode
SRAM RowDecoder
DRAM
1M X 16
1of4096Decode
Ad3-7
1of32
Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
Upper Byte
Lower Byte
DRAM RowDecoder
16bits
As0-2
1of8Decode
Upper Byte
Lower Byte
RB2
Lower Byte
Upper Byte
Lower Byte
RB1
Ad0-11
X
DQs
WB2
DQ8-15
DQ0-7
DQ8-15
DQ0-7
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| M5M4V16169DRT-15 | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-7 | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-8 | 22182053 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DRT-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
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