參數(shù)資料
型號(hào)： M44C090-H
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Low-Current Microcontroller for Wireless Communication
中文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁數(shù)： 51/63頁
文件大小： 503K
代理商： M44C090-H
M44C890
M44C090
Rev.A4, 14-Dec-01
51 (63)
4.1.1
The U505M has an I
2
C-like two-wire serial interface to
the microcontroller for read and write accesses to the
EEPROM. The U505M is considered to be a slave in all
these applications. That means, the controller has to be
the master that initiates the data transfer and provides the
clock for transmit and receive operations.
Serial Interface
The serial interface is controlled by the M44C890
microcontroller which generates the serial clock and
controls the access via the SCL-line and SDA-line. SCL
is used to clock the data into and out of the device. SDA
is a bidirectional line that is used to transfer data into and
out of the device. The following protocol is used for the
data transfers.
Serial Protocol
Data states on the SDA-line changing only while SCL
is low.
Changes on the SDA-line while SCL is high are
interpreted as START or STOP condition.
A START condition is defined as high to low transi-
tion on the SDA-line while the SCL-line is high.
A STOP condition is defined as low to high transition
on the SDA-line while the SCL-line is high.
Each data transfer must be initialized with a START
condition and terminated with a STOP condition. The
START condition wakes the device from standby
mode and the STOP condition returns the device to
standby mode.
A receiving device generates an acknowledge (A)
after the reception of each byte. This requires an
additional clock pulse, generated by the master. If the
reception was successful the receiving master or slave
device pulls down the SDA-line during that clock
cycle. If an acknowledge is not detected (N) by the
interface in transmit mode, it will terminate further
data transmissions and go into receive mode. A master
device must finish its read operation by a non-ac-
knowledge and then send a stop condition to bring the
device into a known state.
Start
condition
Data
valid
Data
change
Data/
acknowledge
valid
Stop
condition
13884
SCL
SDA
Stand
by
Stand
–
by
Figure 61. I
2
C protocol
Before the START condition and after the STOP
condition the device is in stand-by mode and the SDA
line is switched as input with pull-up resistor.
The control byte that follows the START condition de-
termines the following operation. It consists of the
5-bit row address, 2 mode control bits and the READ
/ NWRITE bit that is used to control the direction of
the following transfer. A
”
0
”
defines a write access
and a
”
1
”
a read access.
Control byte format:
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááá
áááááááááááááá
áááááááááááááááááááááá
áááááááááááááááááááááá
A2
A1
A0
ááá
ááá
ááááááá
ááááááá
ááááááá
áááááááááááááááááááááááááááááááá
Start
A4
C1
R/NW
A3
Ackn
C0
áááááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááááá
áá
ááá
áááá
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