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參數(shù)資料
| 型號： | M44C090-H |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 38/63頁 |
| 文件大?。?/td> | 503K |
| 代理商： | M44C090-H |
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M44C890
M44C090
Rev.A4, 14-Dec-01
38 (63)
3.3.3
SSI Features:
Synchronous Serial Interface (SSI)
2 and 3 wire NRZ
2 wire mode (I
2
C compatible)
(additional internal 2 wire link for multi-chip
packaging solutions)
With Timer 2:
Biphase modulation
Manchester modulation
pulse-width demodulation
Burst modulation
SSI Peripheral Configuration
The synchronous serial interface (SSI) can be used either
for serial communication with external devices such as
EEPROMs, shift registers, display drivers, other
microcontrollers, or as a means for generating and
capturing on-chip serial streams of data. External data
communication takes place via the Port 4 (BP4)
multi-functional port which can be software configured
by writing the appropriate control word into the P4CR
register. The SSI can be configured in any one of the
following ways:
a)
communication with one data terminal and one shift
clock. The SSI uses the Port BP43 as a bidirectional serial
data line (SD) and BP40 as shift clock line (SC).
2-wire external interface for bidirectional data
b)
and output of serial data, with a serial input data terminal
3-wire external interface for simultaneous input
(SI), a serial output data terminal (SO) and a shift clock
(SC). The SSI uses BP40 as shift clock (SC), while the
serial data input (SI) is applied to BP43 (configured in
P4CR as input!). Serial output data (SO) in this case is
passed through to BP42 (configured in P4CR to T2O) via
the Timer 2 output stage (T2M2 configured in mode 6).
c)
together with Timer 2 is capable of performing a variety
of data modulation and functions (see Timer Section).
The modulating data is converted by the SSI into a
continuous serial stream of data which is in turn
modulated in one of the timer functional blocks.
Timer/SSI combined modes
–
the SSI used
d)
as an interchip data interface for use in single package
multi
–
chip modules or hybrids. For such applications, the
SSI is provided with two dedicated pads (MCL_SD and
MCL_SC) which act as a two-wire chip-to-chip link. The
MCL can be activated by the MCL control bit. Should
these MCL pads be used by the SSI, the standard SD and
SC pins are not required and the corresponding Port 4
ports are available as conventional data ports.
General SSI Operation
Multi-chip link (MCL)
–
the SSI can also be used
The SSI is comprised essentially of an 8-bit shift register
with two associated 8-bit buffers
–
the receive buffer
(SRB) for capturing the incoming serial data and a trans-
mit buffer (STB) for intermediate storage of data to be
serially output. Both buffers are directly accessable by
software. Transferring the parallel buffer data into and out
of the shift register is controlled automatically by the SSI
control, so that both single byte transfers or continuous bit
streams can be supported.
14103
8-bit Shift Register
MSB
LSB
Shift_CL
SO
SIC1
SIC2
SISC
SC
Control
STB
SRB
SI
Timer 2
Output
INT3
SC
I/O
–
bus
I/O-bus
SSI-Control
TOG2
POUT
T1OUT
SYSCL
SO
SI
MCL_SC
SD
MCL_SD
Transmit
Buffer
Receive
Buffer
SCI
/2
Figure 43. Block diagram of the synchronous serial interface
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