參數(shù)資料
型號(hào)： M44C090-H
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Low-Current Microcontroller for Wireless Communication
中文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁(yè)數(shù)： 43/63頁(yè)
文件大?。?/td> 503K
代理商： M44C090-H
M44C890
M44C090
Rev.A4, 14-Dec-01
43 (63)
(2)
(1)
(4)
(4)
(3)
(1)
Start
condition
Data
valid
Data
change
Data
valid
Stop
condition
13832
SC
SD
Figure 49. I
2
C bus protocol 1
Bus not busy (1)
Both data and clock lines remain HIGH.
Start data transfer (2)
A HIGH to LOW transition of the SD line while
the clock (SC) is HIGH defines a START
condition.
Stop data transfer (3)
A LOW to HIGH transition of the SD line while
the clock (SC) is HIGH defines a STOP condition.
Data valid (4)
The state of the data line represents valid data
when, after START condition, the data line is
stable for the duration of the HIGH period of the
clock signal.
Acknowledge
All address and data words are serially transmitted
to and from device in eight
–
bit words. The
receiving device returns a zero on the data line
during the ninth clock cycle to acknowledge word
receipt.
13833
SC
SD
Start
1
n
8
9
1st Bit
8th Bit
ACK
Stop
Figure 50. I
2
C bus protocol 2
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI
buffer register status (i.e., transmit buffer empty or
receive buffer full) at the end of SSI data telegram or on
the falling edge of the SC/SD pins on Port 4 (see P4CR).
SSI interrupt selection is performed by the
I
nterrupt
F
unctio
N
control bit (IFN). The SSI interrupt is usually
used to synchronize the software control of the SSI and
inform the controller of the present SSI status. The Port
4 interrupts can be used together with the SSI or, if the SSI
itself is not required, as additional external interrupt
sources. In either case this interrupt is capable of waking
the controller out of sleep mode.
To enable and select the SSI relevant interrupts use the
SSI interrupt mask (SIM) and the Interrupt Function
(IFN) while the Port 4 interrupts are enabled by setting
appropriate control bits in P4CR register.
Modulation
If the shift register is used together with Timer 2 for
modulation purposes, the 8-bit synchronous mode must
be used. In this case, the unused Port 4 pins can be used
as conventional bidirectional ports.
The modulation stage, if enabled, operates as soon as the
SSI is activated (SIR=0) and ceases when deactivated
(SIR=1).
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