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| 型號： | M44C090-H |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 15/63頁 |
| 文件大?。?/td> | 503K |
| 代理商： | M44C090-H |
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M44C890
M44C090
Rev.A4, 14-Dec-01
15 (63)
2.5
2.5.1
Clock Generation
Clock Module
The M44C090 / M44C890 contains a clock module with
4 different internal oscillator types: two RC-oscillators,
one 4-MHz crystal oscillator and one 32-kHz crystal
oscillator. The pins OSC1 and OSC2 are the interface to
connect a crystal either to the 4-MHz, or to the 32-kHz
crystal oscillator. OSC1 can be used as input for external
clocks or to connect an external trimming resistor for the
RC-oscillator 2. All necessary circuitry except the crystal
and the trimming resistor is integrated on-chip. One of
these oscillator types or an external input clock can be
selected to generate the system clock (SYSCL).
In applications that do not require exact timing, it is
possible to use the fully integrated RC-oscillator 1
without any external components. The RC-oscillator 1
center frequency tolerance is better than
±
50%. The
RC-oscillator 2 is a trimmable oscillator whereby the
oscillator frequency can be trimmed with an external
resistor attached between OSC1 and V
DD
. In this
configuration, the RC-oscillator 2 frequency can be
maintained stable to within a tolerance of
±
15% over the
full operating temperature and voltage range.
The clock module is programmable via software with the
clock management register (CM) and the system
configuration register (SC). The required oscillator
configuration can be selected with the OS1-bit and the
OS0-bit in the SC-register. A programmable 4-bit divider
stage allows the adjustment of the system clock speed. A
special feature of the clock management is that an
external oscillator may be used and switched on and off
via a port pin for the power-down mode. Before the
external clock is switched off, the internal RC-oscillator
1 must be selected with the CCS-bit and then the SLEEP
mode may be activated. In this state an interrupt can wake
up the controller with the RC-oscillator, and the external
oscillator can be activated and selected by software. A
synchronization stage avoids too short clock periods if the
clock source or the clock speed is changed. If an external
input clock is selected, a supervisor circuit monitors the
external input and generates a hardware reset if the
external clock source fails or drops below 500 kHz for
more than 1 msec.
Ext. clock
ExIn
ExOut
Stop
RC oscillator2
RCOut2
Stop
R
Trim
4
–
MHz oscillator
Oscin
Oscout
4Out
Stop
Oscin
Oscout
32
–
kHz oscillator
Oscin
Oscout
32Out
RC
oscillator 1
RCOut1
Control
Stop
IN1
IN2
Cin
/2
/2
/2
/2
Divider
Sleep
WDL
Osc
–
Stop
NSTOP
CCS
CSS1
CSS0
CM:
BOT
–
–
–
OS1
OS0
SUBCL
SYSCL
SC:
OSC1
OSC2
Cin/16
32 kHz
Figure 14. Clock module
Table 5 Clock modes
Mode
Clock Source for SYSCL
CCS = 1
Clock Source for SUBCL
OS1
0
OS0
1
CCS = 0
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RC-oscillator 2 with
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