參數(shù)資料
型號: M44C090-H
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Low-Current Microcontroller for Wireless Communication
中文描述: 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝: SSO-20
文件頁數(shù): 35/63頁
文件大?。?/td> 503K
代理商: M44C090-H
M44C890
M44C090
Rev.A4, 14-Dec-01
35 (63)
Timer 2 Mode Register 1 (T2M1)
Address:
7
hex
Subaddress:
1
hex
Bit 3
T2D1
Bit 2
T2D0
Bit 1
T2MS1
Bit 0
T2MS0
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áááááááááááááááááááááááá
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áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááá
áááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
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áááááááááááááááááááááááááááááááá
áááááááááááááááááááááá
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T2M1
1
imer
2
D
uty cycle bit
0
Reset value: 1111b
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Clock Output (POUT)
4-bit counter overflow (OVF1)
12-bit compare counter, the DCG
have to be bypassed in this mode
4-bit compare output (CM1)
8-bit compare counter with 4-bit
programmable prescaler and duty-
cycle generator
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler run, the
counter 2/1 starts after writing
mode 3
4-bit compare output (CM1)
ááááááááááá
ááááááááááá
1
1
Bypassed (DCGO0)
1
0
Duty cycle 1/1 (DCGO1)
0
1
Duty cycle 1/2 (DCGO2)
0
0
Duty cycle 1/3 (DCGO3)
á
á
á
á
á
á
á
á
á
1
1
1
/ 3
/ 4
T2MS0
T
imer
2
M
ode
S
elect bit
0
8-bit compare counter clocked by
SYSCL or the external clock input
4
0
0
Duty-Cycle Generator
The duty-cycle generator generates duty cycles from 25%, 33% or 50%. The frequency at the duty-cycle generator
output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional
programmable prescaler for Timer 2.
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
13807
Figure 42. DCG output signals
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