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參數(shù)資料
| 型號： | M38C59MF-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 40/75頁 |
| 文件大?。?/td> | 995K |
| 代理商： | M38C59MF-XXXHP |
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Rev.2.00
Nov 23, 2005
page 45 of 73
REJ03B0028-0200
38C5 Group
Fig. 41 Block diagram of LCD controller/driver
f(X
CIN
)/32
φ
SOURCE
/8192
COM
0
COM
1
COM
2
COM
3
V
SS
V
L3
P2
3
/SEG
3
P2
2
/SEG
2
P2
1
/SEG
1
P2
0
/SEG
0
“0
”
“1
”
LCDCK
2
V
L2
V
L1
COM
4
/
SEG
35
COM
5
/
SEG
34
COM
6
/
SEG
33
COM
7
/
SEG
32
COM
4
/
SEG
35
COM
5
/
SEG
34
COM
7
/
SEG
32
C
1
C
2
VL3
connection
bit
VCC
(Note
1)
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
Data
bus
Timing
controller
Common
driver
Bias
control
LCDCK
count
source
selection
bit
LCD
circuit
divider
division
ratio
selection
bits
Bias
control
bit
LCD
enable
bit
Duty
ratio
selection
bits
Selector
LCD
display
RAM
Address
0862
16
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Common
driver
Common
driver
Common
driver
Selector
Segment
driver
Segment
driver
Voltage
multiplier
control
bit
Level
shift
Level
shift
Level
shift
Level
shift
Common
driver
Common
driver
Common
driver
Common
driver
Address
0863
16
Address
0840
16
Address
0841
16
Address
0842
16
Address
0843
16
LCD
divider
Notes
1:
LCDCK
is
the
clock
for
the
LCD
timing
controller.
φSOURCE
represents
the
supply
source
of
internal
clock
φ.
X
IN
input:
in
the
middle-
or
high-speed
mode,
internal
on-chip
oscillator
divided
by
4
in
the
on-chip
oscillator
mode,
and
Sub
clock
in
the
low-speed
mode.
2:
When
the
voltage
multiplier
circuit
is
not
used
(bit
0
of
LCD
mode
register
2
=
“0
”),
the
C
1
and
C
2
pins
function
as
input
ports
P7
0
/INT
01
,P7
1
/INT
11
.
(Note
2)
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