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| 型號： | M38C59MF-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 15/75頁 |
| 文件大小： | 995K |
| 代理商： | M38C59MF-XXXHP |
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Rev.2.00
Nov 23, 2005
page 22 of 73
REJ03B0028-0200
38C5 Group
INTERRUPTS
Interrupts occur by seventeen sources: six external, ten internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by program. Interrupt re-
quest bits can be cleared by program, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupt requests occur at the same
time, the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
2. The interrupt disable flag is set to “1” and the corresponding
interrupt request bit is set to “0”.
3. The interrupt jump destination address is read from the vector
table into the program counter.
s Notes on Interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X control register (address 2E16)
Timer Y mode register (address 3816)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A16)
When not requiring the interrupt occurrence synchronous with these
setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge selection bit (polarity switch bit) or the inter-
rupt source selection bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Source
Reset (Note 2)
INT0 (INT00 or
INT01) (Note 3)
INT1 (INT10 or
INT11) (Note 3)
INT2
Key input
(key-on wakeup)
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2
CNTR0
Timer Y
CNTR1
A/D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses (Note 1)
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling
edge of INT0 input
At detection of either rising or falling
edge of INT1 input
At detection of either rising or falling
edge of INT2 input
At falling of ports P20–P23, P44–P47
input logical level AND
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit
shift or transmit buffer is empty
At completion of serial I/O2 data trans-
mit/receive
At detection of either rising or falling
edge of CNTR0 input
At timer Y underflow
At detection of either rising or falling
edge of CNTR1 input
At completion of A/D conversion
At BRK instruction execution
Non-maskable
External interrupt (active edge selectable)
Valid when INT2 interrupt is selected
External interrupt (active edge selectable)
Valid when key input interrupt is selected
External interrupt (falling valid)
Valid only when serial I/O1 is selected
External interrupt (active edge selectable)
Non-maskable software interrupt
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: INT0 (INT00 or INT01), INT1 (INT10 or INT11) input pins are selected by the interrupt edge selection register (INTEDGE).
Table 7 Interrupt vector addresses and priority
Remarks
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