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參數(shù)資料
| 型號： | M38C59MF-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 20/75頁 |
| 文件大?。?/td> | 995K |
| 代理商： | M38C59MF-XXXHP |
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Rev.2.00
Nov 23, 2005
page 27 of 73
REJ03B0028-0200
38C5 Group
Output waveform of Timer 3 PWM0 or Timer 4 PWM1
256
ts
256
ts
256
ts
256
ts
n ts
PWM01 register = “002”
n: Setting value of Timer 3 or Timer 4
ts: One period of Timer 3 count source or Timer 4 count source
PWM01 register (address 002416) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3)
(n+1) ts
PWM01 register = “012”
PWM01 register = “102”
PWM01 register = “112”
Short interval
4 256
ts
Long interval
Interrupt request
q Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for
the count source. The count source of the frequency divider is switched
to XIN, XCIN, or the on-chip oscillator (ROSC) divided by 4 in the on-
chip oscillator mode by the CPU mode register. The frequency di-
vider is controlled by each timer division ratio selection bit. The divi-
sion ratio can be selected from as follows;
1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(ROSC)/4.
Stop a timer to switch the division of frequency.
q Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register.
When XCIN is selected as the count source, a pulse input from XCIN
can be counted. Also, by the timer 12 mode register, each time timer
2 underflows, the signal of which polarity is inverted can be output
from P72/T2OUT pin.
At reset, all bits of the timer 12 mode register are set to “0,” timer 1 is
set to “FF16”, and timer 2 is set to “0116”.
When executing the STP instruction, previously set the wait time at
return.
q Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. Also, by the timer 34 mode register, each
time timer 3 or timer 4 underflows, the signal of which polarity is
inverted can be output from P73/T3OUT pin or P74/T4OUT pin.
q Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
A PWM rectangular waveform corresponding to the 10-bit accuracy
can be output from the P73/PWM0 pin and P74/PWM1 pin by set-
ting the timer 34 mode register and PWM01 register (refer to Figure
23).
One output pulse is the short interval. Four output pulses are the
long interval. The “n” is the value set in the timer 3 (address 002216)
or the timer 4 (address 002316). The “ts” is one period of timer 3 or
timer 4 count source. “H” width of the short interval is obtained by n
ts.
However, in the long interval, “H” width of output pulse is extended
for ts which is set by the PWM01 register (address 002416).
s Notes on Timer 3 PWM0 Mode, Timer 4 PWM1
Mode
qWhen PWM output is suspended after starting PWM output, de-
pending on the level of the output pulse at that time to resume an
output, the delay of the one section of the short interval may be
needed.
Stop at “H”: No output delay
Stop at “L”: Output is delayed time of 256 ts
qIn the PWM mode, the follows are performed every cycle of the
long interval (4 256 ts).
Generation of timer 3, timer 4 interrupt requests
Update of timer 3, timer 4
s Writing to Timer 2, Timer 3, Timer 4
When writing to the latch only, if the write timing to the reload latch
and the underflow timing are almost the same, the value is set into
the timer and the timer latch at the same time. In this time, counting
is stopped during writing to the reload latch.
Fig. 23 Waveform of PWM0 and PWM1
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