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| 型號： | M38C59MF-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 22/75頁 |
| 文件大小： | 995K |
| 代理商： | M38C59MF-XXXHP |
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Rev.2.00
Nov 23, 2005
page 29 of 73
REJ03B0028-0200
38C5 Group
16-bit Timer
Read and write operation on 16-bit timer must be performed for both
high and low-order bytes. When reading a 16-bit timer, read the high-
order byte first. When writing to a 16-bit timer, write the low-order
byte first. The 16-bit timer cannot perform the correct operation when
reading during the write operation, or when writing during the read
operation.
Fig. 25 Structure of timer related register
1/2
1/4
INT2
D Q
Latch
CNTR0
INT00/INT01
0
s
4/f(XIN)
8/f(XIN)
16/f(XIN)
XcIN
XIN
2
Timer X output
control bit 1
Timer X output
control bit 2
“010”
S
Q
T
S
P65/TXOUT1/(LED3)
S
Q
T
R
S
Q
T
R
P63/TXOUT2/(LED1)
Timer X output 2 edge
switch bit
φSOURCE
φ SOURCE:
Delay circuit 1/2
X 2
Trigger for IGBT control bit
INT10/INT11
Data bus
Frequency
divider
Noise filter sampling
clock selection bit
Timer X interrupt
request
Equal
Pulse width
measurement mode
Timer X count
stop bit
Compare register 1
(low-order)(8)
Compare register 1
(high-order)(8)
Pulse output mode
CNTR0 active
edge switch bits
Timer X operating
mode bits
CNTR0
interrupt request
Extend latch
(2)
Extend counter
(2)
Timer X write
control bit
Timer 1 interrupt
Data for control of event counter window
Delay time
selection bits
Noise filter
(4 times same
levels judgment)
INT0
interrupt request
Count source selection bit
Clock for Timer X
Frequency divider
Timer X frequency
division selection bits
Both edges
detection
Timer X operating
mode bits
Timer X operating
mode bits
Delay
circuit
Timer X (low-order) latch (8)
Timer X (low-order)(8)
Timer X (high-order) latch (8)
Timer X (high-order)(8)
Edge
selection *
Edge
selection *
Edge
detection
Edge
selection *
Compare register 2
(low-order)(8)
Compare register 2
(high-order)(8)
Compare register 3
(low-order)(8)
Compare register 3
(high-order)(8)
Timer X output 2 selection bit
P63 latch
P63
direction
register
IGBT output mode
PWM mode
Timer X output 1 edge
switch bit
Timer X output 1 selection bit
P65 latch
P65
direction
register
“000”
“001”
“010”
“011”
“101”
“0”
“1”
“100”
“00”
“01”
“10”
“11”
“00”
“01”
“10”
“11”
“1”
“0”
“1”
“0”
“1”
“010”
“0”
“1”
“0”
“000”
“001”
“011”
“100”
“101”
represents the supply source of internal clock
φ.
XIN input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and
Sub clock in the low-speed mode.
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