參數(shù)資料
型號(hào)： M38C59MF-XXXHP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 32/75頁(yè)
文件大?。?/td> 995K
代理商： M38C59MF-XXXHP
Rev.2.00
Nov 23, 2005
page 38 of 73
REJ03B0028-0200
38C5 Group
Fig. 34 Structure of serial I/O1 related registers
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 status register
Serial I/O1 control register
b0
BRG count source selection bit (CSS)
0:
φSOURCE
1:
φSOURCE/4
b7
UART control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
b0
(SIO1STS : address 001916)
(SIO1CON : address 001A16)
(UARTCON : address 001B16)
φ SOURCE: represents the supply source of internal clock φ.
XIN input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and
Sub clock in the low-speed mode.
(Note)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P40 to P43 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P40 to P43 operate as serial I/O pins)
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
SRDY1 output enable bit (SRDY)
0: P43 pin operates as ordinary I/O pin
1: P43 pin operates as SRDY1 output pin
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected.
External clock input divided by 16 when UART is selected.
Not used (return “1” when read)
P41/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Not used (returns “1” when read)
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Framing error flag (FE)
0: No error
1: Framing error
Parity error flag (PE)
0: No error
1: Parity error
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
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