參數(shù)資料
型號: M38C24M4A-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 3/102頁
文件大?。?/td> 1369K
代理商: M38C24M4A-XXXFP
Rev.2.00
May 28, 2004
page 100 of 100
38C2 Group (A Version)
Notes on Reset Circuit
1. Reset input voltage control
Make sure that the reset input voltage is less than 0.2 Vcc for Vcc(min).
2. Countermeasures for reset signal slow rising
In case where the RESET signal rise time is long, connect a ceramic
capacitor or others across the RESET pin and the Vss pin. Use a
1000 pF or more capacitor for high frequency use. When connecting
the capacitor, note the following:
Make the length of the wiring which is connected to a capacitor as
short as possible.
Be sure to verify the operation of application products on the user
side.
<Reason>
If the several nanosecond or several ten nanosecond impulse noise
enters the RESET pin, it may cause a microcomputer failure.
3. Port state immediately after reset
Table 1 shows the each pin state during RESET pin is “L”.
Table 1 Each pin state during RESET pin is “L”
Pin name
P0–P2 (SEG0–SEG23)
P3, P4, P5, P60–P62
COM0–COM3
Pin state
Input mode (with pull-up)
Input mode (high-impedance)
Vcc level input
4. Frequency relation of f(XIN) and f(
φ)
The frequency relation of f(XIN) and f(
φ) is f(XIN) = 8 f(φ).
Notes on Reset Circuit
1. Mode transition
(1) Both the main clock (XIN-XOUT) and sub-clock (XCIN-XCOUT) need
time for the oscillations to stabilize. The mode transition between
middle-/high-speed and low-speed mode must be performed af-
ter the corresponding clock becomes stable. The sub-clock, needs
extra time to stabilize particularly when executing operations af-
ter power-on and stop mode. The main and sub clocks require
the following condition for mode transition.
f(XIN) > 3 f(XCIN)
(2) The all modes can be switched to the stop mode or the wait mode
and return to the source mode when the stop mode or the wait
mode is ended.
2. State transitions of system clock
When the mode is switched from frequency/2/4/8 to the low-speed
mode, or the opposite is performed, change CM7 (bit 7 of system
clock control bits of CPU mode register (address 003B16)) at first,
and then, change CM6 (bit 6 of system clock control bits of CPU
mode register (address 003B16)) after the oscillation of the changed
mode is stabilized.
3. Wait mode
Timer and LCD operate in the wait mode.
Notes on Oscillation External Output Function
When the signal from the XOUT pin or XCOUT pin of the oscillation
circuit is input directly to the circuit except this MCU and used, the
system operation may be unstabilized.
In order to share the oscillation circuit safely, use the clock output
from P40 and P41 by the oscillation external output function for the
circuits except this MCU.
NOTES ON HARDWARE
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(VCC pin) and GND pin (VSS pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be lo-
cated too far from the pins to be connected, a ceramic capacitor of
0.01
F–0.1F is recommended.
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