Rev.2.00
May 28, 2004
page 26 of 100
38C2 Group (A Version)
16-bit Timer
q Frequency Divider For Timer
Each timer X and timer Y have the frequency dividers for the count
source. The count source of the frequency divider is switched to XIN
or XCIN by the CPU mode register. The division ratio of each timer
can be controlled by each timer division ratio selection bit. The divi-
sion ratio can be selected from as follows;
1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN); or f(XCIN).
q Timer X
The timer X count source can be selected by setting the timer X mode
register. When f(XCIN) is selected as the count source, counting can
be performed regardless of XCIN oscillation. However, when XCIN is
stopped, the external pulse input from XCIN pin is counted.
The timer X operates as down-count. When the timer contents reach
“000016”, an underflow occurs at the next count pulse and the timer
latch contents are reloaded. After that, the timer continues count-
down. When the timer underflows, the interrupt request bit correspond-
ing to the timer X is set to “1”.
Six operating modes can be selected for timer X by the timer X mode
register and timer X control register.
(1) Timer Mode
The count source can be selected by setting the timer X mode regis-
ter. In this mode, timer X operates as the 18-bit counter by setting the
timer X register (extension).
(2) Pulse Output Mode
Pulses of which polarity is inverted each time the timer underflows
are output from the TXOUT pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set the port sharing the TXOUT pin to output
mode.
(3) IGBT Output Mode
After dummy output from the TXOUT pin, count starts with the INT0
pin input as a trigger. In the case that the timer X output edge switch
bit is “0”, when the trigger is detected or the timer X underflows, “H” is
output from the TXOUT pin. And then, when the count value corre-
sponds with the compare register value, the TXOUT output becomes
“L”.
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT0 signal can use 4
types of delay time by a delay circuit.
When using this mode, set the port sharing the INT0 pin to input
mode and set the port sharing the TXOUT pin to output mode.
When the timer X output control bit 1 or 2 of the timer X control reg-
ister is set to “1”, the timer X count stop bit is fixed to “1” forcibly by
the interrupt signal of INT1 or INT2. And then, the TXOUT output can
be set to “L” forcibly at the same time that the timer X stops counting.
Do not write “1” to the timer X register (extension) when using the
IGBT output mode.
(4) PWM Mode
IGBT dummy output, an external trigger with the INT0 pin and output
control with pins INT1 and INT2 are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer X set value. In
the case that the timer X output edge switch bit is “0”, the “H” interval
is specified by the compare register set value.
When using this mode, set the port sharing the TXOUT pin to output
mode.
Do not write “1” to the timer X register (extension) when using the
PWM mode.
Output waveform of Timer 3 PWM0 or Timer 4 PWM1
256
ts
256
ts
256
ts
256
ts
n ts
PWM01 register = “002”
n: Setting value of Timer 3 or Timer 4
ts: One period of Timer 3 count source or Timer 4 count source
PWM01 register (address 002416) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3)
(n+1) ts
PWM01 register = “012”
PWM01 register = “102”
PWM01 register = “112”
Short interval
4 256
ts
Long interval
Interrupt requestInterrupt request
Fig. 21 Waveform of PWM0 and PWM1