Rev.2.00
May 28, 2004
page 15 of 100
38C2 Group (A Version)
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Common
Input/Output
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Output
I/O format
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD common output
Non-port function
LCD segment
output
Serial I/O2 function I/O
External interrupt input
Timer X output
Timer 2 output
Timer X function input
A-D conversion
input
External interrupt input
Timer 3 output
Timer 4 output
PWM output
Serial I/O1
function I/O
Timer Y function input
Sub-clock oscillation circuit
Related SFRs
Segment output disable
register 1
Segment output disable
register 2
Segment output disable
register 3
PULL register
Serial I/O2 control register
Serial I/O2 status register
UART2 control register
PULL register
Interrupt edge selection
register
PULL register
Timer X mode register
Timer 12 mode register
PULL register
Timer X mode register
PULL register
A-D control register
PULL register
A-D control register
Timer Y mode register
PULL register
Interrupt edge selection
register
PULL register
Timer 12 mode register
PULL register
Serial I/O1 control register
Serial I/O1 status register
UART1 control register
PULL register
Timer Y mode register
PULL register
CPU mode register
LCD mode register
Ref. No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(7)
(11)
(10)
(11)
(7)
(9)
(12)
(13)
(14)
(15)
(7)
(16)
(17)
(18)
Table 6 List of I/O port function
Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
P00/SEG0 –
P03/SEG3
P04/SEG4 –
P07/SEG7
P10/SEG8 –
P17/SEG15
P20/SEG16 –
P25/SEG21
P26/SEG22/VL1
P27/SEG23/VL2
P30/SRDY2
P31/SCLK2
P32/TxD2
P33/RxD2
P34/INT2
P35/TXOUT
P36/T2OUT/
φ
P37/CNTR0
P40/OOUT0/AN0
P41/OOUT1/AN1
P42/AN2–
P45/AN5
P46/RTP0/AN6
P47/RTP1/AN7
P50/INT0
P51/INT1
P52/T3OUT/PWM0
P53/T4OUT/PWM1
P54/RxD1
P55/TxD1
P56/SCLK1
P57/SRDY1
P60/CNTR1
P61/XCIN
P62/XCOUT
COM0–COM3
Pin
Key input
(key-on wakeup)
interrupt input
LCD power
input
Oscillation
external
output
Real time
port function
output
Key input
(key-on wakeup)
interrupt input