參數(shù)資料
型號(hào)： M38C24M4A-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 23/102頁(yè)
文件大?。?/td> 1369K
代理商： M38C24M4A-XXXFP
Rev.2.00
May 28, 2004
page 27 of 100
38C2 Group (A Version)
Fig. 22 Waveform of PWM/IGBT
(5) Event Counter Mode
The timer counts signals input through the CNTR0 pin. In this mode,
timer X operates as the 18-bit counter by setting the timer X register
(extension). When using this mode, set the port sharing the CNTR0
pin to input mode.
In this mode, the window control can be performed by the timer 1
underflow. When the bit 5 (data for control of event counter window)
of the timer X mode register is set to “1”, counting is stopped at the
next timer 1 underflow. When the bit is set to “0”, counting is re-
started at the next timer 1 underflow.
(6) Pulse Width Measurement Mode
In this mode, the count source is the output of frequency divider for
timer. In this mode, timer X operates as the 18-bit counter by setting
the timer X register (extension). When the bit 6 of the CNTR0 active
edge switch bits is “0”, counting is executed during the “H” interval of
CNTR0 pin input. When the bit is “1”, counting is executed during the
“L” interval of CNTR0 pin input. When using this mode, set the port
sharing the CNTR0 pin to input mode.
s Notes on Timer X
(1) Write Order to Timer X
In the timer mode, pulse output mode, event counter mode and
pulse width measurement mode, write to the following registers in
the order as shown below;
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
Do not write to only one of them.
When the above mode is set and timer X operates as the 16-bit
counter, if the timer X register (extension) is never set after reset is
released, setting the timer X register (extension) is not required. In
this case, write the timer X register (low-order) first and the timer X
register (high-order). However, once writing to the timer X register
(extension) is executed, note that the value is retained to the reload
latch.
In the IGBT output and PWM modes, do not write “1” to the timer X
register (extension). Also, when “1” is already written to the timer X
register, be sure to write “0” to the register before using.
Write to the following registers in the order as shown below;
the compare register (high- and low-order),
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
It is possible to use whichever order to write to the compare regis-
ter (high- and low-order). However, write both the compare register
and the timer X register at the same time.
(2) Read Order to Timer X
In all modes, read the following registers in the order as shown below;
the timer X register (extension),
the timer X register (high-order),
the timer X register (low-order).
When reading the timer X register (extension) is not required, read
the timer X register (high-order) first and the timer X register (low-
order).
Read order to the compare register is not specified.
If reading to the timer X register during write operation or writing to
it during read operation is performed, normal operation will not be
performed.
(3) Write to Timer X
Which write control can be selected by the timer X write control bit
(b3) of the timer X mode register (address 2F16), writing data to
both the latch and the timer at the same time or writing data only to
the latch. When writing a value to the timer X address to write to the
latch only, the value is set into the reload latch and the timer is
updated at the next underflow. After reset release, when writing a
value to the timer X address, the value is set into the timer and the
timer latch at the same time, because they are written at the same
time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this time,
counting is stopped during writing to the high-order reload latch.
Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
ts
Timer X count
source
Timer X
PWM mode
IGBT output
mode
(n-m+1) tsm ts
(n+1) ts
When the Timer X setting value = n and the compare register setting value = m, and
the period of timer X count souce = ts, the following PWM waveform is output;
Duty : (n-m+1)/(n+1)
Period : (n+1) ts
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