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Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
59
Clock source
selection
f1
f8
f32
fC32
Prescaler 1 (address 008816)
Peripheral data bus
Reload register (8)
Counter (8)
Reload register (8)
Counter (8)
Timer 1 (address 008916)
Timer 1 interrupt
request bit
Figure 1.14.1. Block diagram of timer 1
Timer
The microcomputer has a total of four timers: Timer 1, timer X, timer Y, and timer Z.
The divide-by ratios of all timers and prescalers are determined by 1 / (n + 1) where n = content of the timer
reload register or prescaler reload register.
The timers are down-counters, so that the timer underflows at the next count pulse after it reached the
minimum count of 0, and is reloaded with the content of the timer reload register. Also, when the timer
underflows, the interrupt request bit corresponding to each timer is set to 1.
Timer 1
Timer 1 is an 8-bit timer, which always counts prescaler-1 output. When timer 1 underflows after reaching
the minimum count, the timer 1 interrupt request bit is set.
Prescaler 1 is an 8-bit prescaler, which counts the signal selected with the timer 1 count source select bit.
Prescaler 1 and timer 1 respectively have a prescaler-1 reload register and a timer-1 reload register to
hold their reload values. The value of the prescaler-1 reload register is transferred to prescaler 1 when it
underflows. Similarly, the value of the timer-1 reload register is transferred to timer 1 when it underflows.
Any value written to prescaler 1 (PRE1) is also written to the prescaler-1 reload register at the same time.
Any value written to timer 1 (T1) is also written to the timer-1 reload register at the same time.
When prescaler 1 (PRE1) or timer 1 (T1) is accessed for read, their count value is read out.
Timer 1 always operates in timer mode.
Prescaler 1 counts the selected count source and each time the count clock is applied, the prescaler has
its content decremented by one. After reaching “0016,” prescaler 1 underflows at the next count clock and
is reloaded with the value transferred from the prescaler-1 reload register and starts counting over again.
The divide-by ratio of prescaler 1 is 1 / (n + 1) where n = set value of prescaler 1.
Timer 1 has its content decremented by one each time an underflow signal is received from prescaler 1.
After reaching “0016,” timer 1 underflows at the next count clock and is reloaded with the value transferred
from the timer-1 reload register and starts counting over again.
The divide-by ratio of timer 1 is 1 / (m + 1) where m = set value of Timer 1. Therefore, assuming n = set
value of prescaler 1 and m = set value of timer 1, the divide-by ratio of timer 1 is 1 / ((n + 1) x (m + 1)).