參數(shù)資料
型號(hào)： M30101F3FP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO42
封裝： PLASTIC, SSOP-42
文件頁數(shù)： 108/125頁
文件大?。?/td> 1608K
代理商： M30101F3FP
Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
83
Example of transmit timing (when internal clock is selected)
Example of receive timing (when external clock is selected)
Clock synchronous serial I/O mode
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32, fc)
n: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings:
Internal clock is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
1 / fEXT
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
The above timing applies to the following settings:
External clock is selected.
CLK polarity select bit = “0”.
fEXT: frequency of external clock
Transferred from UARTi receive register
to UARTi receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D0 D1 D2 D3
D4 D5
D6
D7
D0
D1 D2
D3 D4
D5
Shown in ( ) are bit symbols.
Meet the following conditions when the CLKi input level
before data reception = “H”
Transmit enable bit
“1”
Receive enable bit
“1”
Dummy data write to UARTi transmit buffer register
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc
TCLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UARTi transmit buffer
register
Transferred from UARTi transmit buffer register to UARTi transmit
register
Cleared to “0” when interrupt request is accepted, or cleared by software
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5 D6 D7
Figure 1.15.7. Typical transmit/receive timings in clock synchronous serial I/O mode
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