參數(shù)資料
型號(hào): M30101F3FP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO42
封裝: PLASTIC, SSOP-42
文件頁數(shù): 105/125頁
文件大?。?/td> 1608K
代理商: M30101F3FP
Serial I/O
Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
80
UARTi transmit/receive control register 1
Symbol
Address
When reset
UiC1(i=0,1)
00A516,00AD16
0216
b7
b6
b5
b4
b3 b2
b1
b0
Bit name
Bit
symbol
Function
(During UART mode)
Function (Note 1)
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
(Note)
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: When using multiple pins to output the transfer clock, the following requirements must be met:
UART1 internal/external clock select bit (bit 3 at address 00A016) = “0”.
UART transmit/receive control register 2
Symbol
Address
When reset
UCON
00B016
0016
b7
b6
b5 b4
b3
b2
b1
b0
Bit
name
Bit
symbol
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK0 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Fixed to “0”
U0IRS
U1IRS
U0RRM
CLK/CLKS select
bit 1 (Note 1)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Note : As for the UART1, set the RXD1 input port select bit before setting this bit to reception enabled.
When the receive enable bit is set for enabled in M30100, select P37 with RXD1 input port
select bit.
W
R
W
R
Invalid
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
U1RRM
Invalid
RXD1EN
0 : P37
1 : P35
RXD1 input port
select bit
0 : P37
1 : P35
Figure 1.15.5. Serial I/O-related registers (3)
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