參數(shù)資料
型號： M30101F3FP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO42
封裝： PLASTIC, SSOP-42
文件頁數(shù)： 46/125頁
文件大?。?/td> 1608K
代理商： M30101F3FP
Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
27
Status Transition of BCLK
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.8.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, division by 8 mode is set. The main clock division select bit 0 (bit 6 at address 000616)
changes to “1” when shifting from high-speed/medium-speed mode to stop mode or at a reset. The follow-
ing shows the operational modes of BCLK. When shifting from low-speed/low power dissipation mode to
stop mode, the value before stop mode is retained.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. Before the user can go from this mode to no division
mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to
low-speed or lower power dissipation mode, sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
(8) Ring oscillator mode
This mode sets the ring oscillator as BCLK. The same as when XIN is the main clock, the modes are no
division, 2-division, 4-division, 8-division, and 16-division.
Note: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
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