參數(shù)資料
型號： M30101F3FP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO42
封裝： PLASTIC, SSOP-42
文件頁數(shù)： 51/125頁
文件大小： 1608K
代理商： M30101F3FP
Power Control
Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
31
CM07=“0“ (Note 1)
CM06=“1”
CM04=“0”
CM04=“1”
(Notes 1, 3)
CM04=“0”
BCLK: f(XIN)/8
CM07=“0” CM06=“1”
CM06=“1”
BCLK: f(RING)/8
CM07=“0”
CM06=“1”
CM22=“1”
BCLK: f(RING)/8
CM07=“0”
CM06=“1”
CM05=“1”
CM22=“1”
BCLK: f(RING)/2
BCLK: f(RING)
CM07=“0”
CM06=“0”
CM05=“1”
CM22=“1”
CM16=“0”
CM17=“0”
CM22=“1”
CM22=“0”
(Note 1)
BCLK: f(RING)/16
BCLK: f(RING)/4
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode (divided-by-8 mode)
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/8
Medium-speed mode
(divided-by-8 mode)
CM07 = “0”
CM06 = “1”
High-speed mode
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mod
(divided-by-2 mode)
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XCIN)
CM07 = “1”
BCLK : f(XCIN)
CM07 = “1”
Main clock is oscillating
Sub clock is oscillating
CM07 = “0”
(Notes 1, 3)
CM07 = “1”
(Note 2)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1” (Note 2)
CM05 = “1”
CM05 = “0”
CM05 = “1”
CM04 = “0”
CM04 = “1”
CM06 = “0”
(Notes 1,3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM17 and CM16 before changing CM06.
Note 4: Transit in accordance with arrow.
Main clock is oscillating
Sub clock is stopped
Ring oscillator mode (divided-by-8 mode)
Main clock is stopped
Sub clock is stopped
Ring oscillator mode
CM05 = “0”
CM05 = “1”
8-division mode
1-division mode (Note 3)
2-division mode (Note 3)
16-division mode (Note 3)
4-division mode (Note 3)
CM07=“0”
CM06=“0”
CM05=“1”
CM22=“1”
CM16=“1”
CM17=“0”
CM07=“0”
CM06=“0”
CM05=“1”
CM22=“1”
CM16=“1”
CM17=“1”
CM07=“0”
CM06=“0”
CM05=“1”
CM22=“1”
CM16=“0”
CM17=“1”
Figure 1.9.2. Clock transition (2)
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