參數(shù)資料
型號(hào)： M30101F3FP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO42
封裝： PLASTIC, SSOP-42
文件頁數(shù)： 32/125頁
文件大小： 1608K
代理商： M30101F3FP
Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
14
Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
Bits 8 to 11: Reserved area
Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
C
D
Z
S
B
O
I
U
IPL
b0
b15
Figure 1.4.2. Flag register (FLG)
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