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Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
23
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. Immediately after reset, only oscillation
starts. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power dissipation. This bit changes to “1” when shifting from high-
speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissi-
pation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that
the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power dissipation. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc, or the clock is derived from the main clock or by
dividing it by 2, 4, 8, or 16. After reset, the BCLK is derived by dividing the clock supplied by the ring
oscillator circuit by 8 after a reset.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed mode to stop mode and at reset. When shifting from low-speed/low power dissipa-
tion mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock
a. f1, f8, f32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral
function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
b. fAD
This clock has the same frequency as the main clock and is used in A-D conversion.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer 1, timer X, timer Y and timer
Z counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.
(7) fRING
This clock is supplied by the ring oscillator circuit. In the ring oscillator mode, the clock divided by the
division ratio selected with the main clock division select bit 0 and bit 1(bit 6 at address 000616, and bit 6
and bit 7 at address 000716) is supplied as BCLK. Immediately after reset, 8 divisions of this clock is
supplied as BCLK. The ring oscillator oscillation can be set to BCLK when oscillation stop is detected or
with the main clock switching bit (bit 2 at address 000C16).