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參數(shù)資料
| 型號： | M29W004T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4Mbit (512Kb x8, Boot Block) Low Voltage Single Supply Flash Memory(4Mb閃速存儲器) |
| 中文描述： | 的4Mb（512KB的× 8，引導(dǎo)塊）低電壓單電源閃存（4Mb的閃速存儲器） |
| 文件頁數(shù)： | 8/30頁 |
| 文件大小： | 199K |
| 代理商： | M29W004T |
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INSTRUCTIONS AND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructionsare made up from
one or more commands to perform Read Memory
Array,ReadElectronicSignature,ReadBlockPro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of
address and data sequences. The in-
structionsrequirefrom 1 to6 cycles,thefirst or first
threeof whichare alwayswrite operationsusedto
initiate the instruction. They are followed by either
furtherwritecycles toconfirmthe first commandor
executethecommandimmediately. Commandse-
quencing must be followed exactly. Any invalid
combinationof commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cy-
cleswhichunlockthe CommandInterface.In addi-
tion, for Erase, instruction confirmation is again
precededby the twoCoded cycles.
Status RegisterBits
P/E.C.statusis indicatedduringexecutionbyData
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mandexecutionwill automaticallyoutputthesefive
StatusRegisterbits.The P/E.C.automaticallysets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables9 and 10.
Data Polling Bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
DuringErase operation,it outputsa ’0’.After com-
pletionof the operation,DQ7will outputthe bit last
programmedor a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourthW pulse for programmingor
after the sixth W pulse for erase. It must be per-
formedat theaddress being programmedor at an
address within the block being erased. If all the
blocksselectedfor erasureare protected,DQ7will
μ
s, andthenreturn to the
previous addressed memory data value. See Fig-
ure11for the Data Pollingflowchartand Figure10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
onablockbeingerasedandthedatavalueon other
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the samebehaviour as
in the normal program execution outside of the
suspendmode.
ToggleBit (DQ6).
WhenProgrammingor Erasing
operationsarein progress,successiveattemptsto
readDQ6willoutputcomplementarydata. DQ6will
toggle following toggling of either G, or E when G
is low. Theoperationis completed when two suc-
cessivereadsyieldthesameoutputdata.The next
readwilloutputthebitlastprogrammedora’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations,that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100
μ
s and then
returnback to Read.DQ6willbe setto ’1’if aRead
operationisattemptedonan EraseSuspendblock.
When erase is suspendedDQ6 will toggle during
programmingoperationsin a block differentto the
blockin Erase Suspend.EitherE or G togglingwill
cause DQ6 to toggle. See Figure 12 for ToggleBit
flowchartand Figure 13 for ToggleBit waveforms.
Hex Code
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
Table7. Commands
8/30
M29W004T, M29W004B
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