參數(shù)資料
型號(hào)： M29W004T
廠(chǎng)商： 意法半導(dǎo)體
英文描述： 4Mbit (512Kb x8, Boot Block) Low Voltage Single Supply Flash Memory(4Mb閃速存儲(chǔ)器)
中文描述： 的4Mb（512KB的× 8，引導(dǎo)塊）低電壓?jiǎn)坞娫撮W存（4Mb的閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 3/30頁(yè)
文件大小： 199K
代理商： M29W004T
MemoryBlocks
The devices feature asymmetricallyblocked archi-
tectureprovidingsystemmemory integration.Both
M29W004TandM29W004Bdeviceshaveanarray
of 11 blocks, one Boot Block of 16K Bytes, two
Parameter Blocks of 8K Bytes, one Main Blockof
32K Bytes and seven Main Blocks of 64K Bytes.
The M29W004T has the Boot Block at the top of
the memory address space and the M29W004B
locates the Boot Block starting at the bottom. The
memorymapsare showedin Figure3. Eachblock
can be erased separately, any combination of
blockscan be specifiedfor multi-blockerase or the
entire chip may be erased. The Erase operations
aremanagedautomaticallybytheP/E.C.Theblock
eraseoperationcan besuspendedinorderto read
from or program to any block not being ersased,
and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected againstProgram or Erase on programming
equipment.All previously protected blocks can be
temporarily unprotectedin the application.
Bus Operations
The following operations can be performed using
theappropriatebus cycles:Read (Array,Electronic
Signature, Block Protection Status), Write com-
mand, OutputDisable, Standby,Reset, BlockPro-
tection, Unprotection, Protection Verify,
Unprotection Verify and Block Temporary Unpro-
tection.See Tables4 and5.
CommandInterface
Instructions,made up of commands written in cy-
cles,can be givento theProgram/EraseController
through a Command Interface (C.I.). For added
dataprotection,program or erase executionstarts
after4 or6cycles.Thefirst,second,fourthandfifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrectcommand or any improper command se-
quencewill reset the deviceto ReadArray mode.
Instructions
Seven instructions are defined to perform Read
Array,AutoSelect(to readtheElectronicSignature
or BlockProtectionStatus),Program,BlockErase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations.The StatusRegisterData Polling, Tog-
gle, Error bits and the RB output may be read at
anytime, duringprogrammingor erase,to monitor
the progress of the operation.
Instructionsare composedof up to sixcycles.The
first two cycles input a Coded sequence to the
CommandInterfacewhichis commonto all instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
outputtheaddresseddata,ElectronicSignatureor
Block Protection Status for Read operations. In
orderto giveadditionaldataprotection,theinstruc-
tionsfor Program and Blockor Chip Erase require
furthercommandinputs.ForaPrograminstruction,
the fourth command cycle inputs the addressand
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Codedsequence before the Erase confirm
commandon the sixthcycle. Erasureof a memory
blockmaybesuspended,inordertoreaddatafrom
anotherblockor to programdata in anotherblock,
and then resumed.
When power is first applied or if Vcc falls below
V
LKO
, the command interface is reset to Read
Array.
SIGNALDESCRIPTIONS
SeeFigure 1 and Table1.
AddressInputs (A0-A18)
. The addressinputsfor
thememoryarrayarelatchedduringa writeopera-
tion on the falling edge of Chip Enable E or Write
EnableW. In Word-wide organisationthe address
lines are A0-A18.When A9 is raised to V
ID
, either
a Read Electronic Signature Manufacturer or De-
viceCode,BlockProtectionStatusor aWriteBlock
Protection or Block Unprotection is enabled de-
pendingon thecombinationof levelsonA0,A1,A6,
A12and A15.
DataInput/Outputs(DQ0-DQ7).
Theinputis data
to be programmed in the memory array or a com-
mand to be written to the C.I. Both are latchedon
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
registerData Polling bitDQ7, the ToggleBits DQ6
and DQ2, the Error bit DQ5or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsaredisabledandwhenRPisat aLowlevel.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers.EHighdeselectsthememory
andreducesthepowerconsumptiontothestandby
level. E can also be used to control writing to the
command register and to the memory array, while
Wremainsat alowlevel.TheChipEnablemustbe
forced to V
ID
duringthe Block Unprotectionopera-
tion.
3/30
M29W004T M29W004B
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