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參數(shù)資料
| 型號(hào)： | M29W004T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4Mbit (512Kb x8, Boot Block) Low Voltage Single Supply Flash Memory(4Mb閃速存儲(chǔ)器) |
| 中文描述： | 的4Mb（512KB的× 8，引導(dǎo)塊）低電壓?jiǎn)坞娫撮W存（4Mb的閃速存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 4/30頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | M29W004T |
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16K BOOTBLOCK
AI02093
7FFFFh
7C000h
7BFFFh
7A000h
79FFFh
40000h
3FFFFh
8K PARAMETER BLOCK
8K PARAMETER BLOCK
32K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
20000h
1FFFFh
10000h
0FFFFh
00000h
M29W004T
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
78000h
77FFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
M29W004B
16K BOOT BLOCK
8K PARAMETER BLOCK
8K PARAMETER BLOCK
32K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
10000h
0FFFFh
08000h
07FFFh
04000h
03FFFh
00000h
64K MAIN BLOCK
06000h
05FFFh
64K MAIN BLOCK
30000h
2FFFFh
Figure 3. MemoryMap and Block Address Table(x8)
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
BlockProtectionand Unprotectionoperations.
WriteEnable(W).
Thisinputcontrolswritingto the
CommandRegisterandAddressand Datalatches.
Ready/Busy Output (RB).
Ready/Busy is an
open-drainoutputandgivestheinternalstateof the
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructionsexcept the Erase Suspendinstruction.
WhenRBis High,the deviceis readyforanyRead,
Program or Erase operation. The RB will also be
Highwhen the memoryis putin EraseSuspendor
Standbymodes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
V
IL
forat leastt
PLPX
. Whentheresetpulseisgiven,
if the memory is in Read or Standbymodes, it will
be available for new operations in t
PHEL
after the
risingedgeof RP. Ifthe memoryis inErase,Erase
Suspend or Program modes the reset will take
t
PLYH
duringwhich theRB signalwill be held at V
IL
.
The end of the memory reset will be indicated by
the rising edge of RB. Ahardware reset during an
Erase or Program operation will corrupt the data
being programmed or the sector(s) being erased.
See Table14 and Figure9.
Temporary block unprotection is made by holding
RP at V
ID
. In this condition previously protected
blocks can be programmedor erased.The transi-
tionof RPfromV
IH
to V
ID
mustslower thant
PHPHH
.
When RP is returned from V
ID
to V
IH
all blocks
temporarily unprotected will be again protected.
See Table15 and Figure9.
V
CC
Supply Voltage.
The power supply for all
operations(Read, Programand Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
4/30
M29W004T, M29W004B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M29W004T-100N1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W004T-100N5TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W004T-100N6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W004T-120N1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory |
| M29W004T-120N5TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory |
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