參數(shù)資料
型號: M12L64164A-7BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VBGA-54
文件頁數(shù): 32/45頁
文件大?。?/td> 831K
代理商: M12L64164A-7BG
ES MT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
32/45
Page Read & Write Cycle at Same Bank @ Burst Length = 4
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid
bus contention.
2. Row precharge will interrupt writing. Last data input , t
RDL
before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
0 1 2 3
4 5 6
7
8
9
10
11
12
13
14 15 16 17
18
19
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
A13
A12
CL =2
CL =3
*Not e 3
Row Active
( A - Bank )
Read
( A - Bank )
Read
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
Precharge
(A - Bank)
: D o n ' t C a r e
Qa0
Qa1
Qb0
Qb1
Dd0
Dd1
t
CDL
Dc1
Dc0
Qa1
Qb0
Qb1
Qb2
Dc1
Dd0
Dd1
Dc0
Qa0
Ra
*Not e 2
C c
Cd
Ra
Ca
Cb
*Not e 1
HIGH
t
R C D
t
RDL
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相關代理商/技術參數(shù)
參數(shù)描述
M12L64164A-7BG2Y 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks
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